Patents by Inventor Masahito Kawabata
Masahito Kawabata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120156948Abstract: There is provided a board connection structure capable of preventing occurrence of a connection failure, which would otherwise be caused by an uneven temperature increase in connection region of circuit boards during thermo-compression bonding.Type: ApplicationFiled: February 22, 2010Publication date: June 21, 2012Applicant: PANASONIC CORPORATIONInventor: Masahito Kawabata
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Publication number: 20110317386Abstract: To provide a connecting structure which can effectively suppress the generation of a crack and an exfoliation of a terminal.Type: ApplicationFiled: December 8, 2009Publication date: December 29, 2011Applicant: PANASONIC CORPORATIONInventor: Masahito Kawabata
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Publication number: 20110294315Abstract: Provided are a circuit board module and an electronic device provided with the same capable of increasing the strength of a card connector, with the configuration that the card connector is mounted to have a specific space from the board. The circuit board module is provided with a card connector portion 40 which includes a card insertion port from which a card C1 having at least one contact is inserted, and a housing chamber 42 which is formed to be communicated with the card insertion port to contain the card C1 therein; and a circuit board 10 having a surface which supports the card connector portion 40.Type: ApplicationFiled: November 17, 2009Publication date: December 1, 2011Applicant: PANASONIC CORPORATIONInventors: Masahito Kawabata, Seiji Yamaguchi
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Publication number: 20110286194Abstract: To provide a connection structure in which terminals having different functions can be connected separately in an insulation state while suppressing the generation of problems such as a crack or an exfoliation of the terminal, a circuit device having the connection structure and an electronic equipment having the circuit device. A connection structure 30 for electrically and mechanically connecting between a connector board 20 and a circuit board 10, includes a frame 31 which at least has a first connection surface 31A connected to the connector board 20.Type: ApplicationFiled: November 17, 2009Publication date: November 24, 2011Applicant: PANASONIC CORPORATIONInventor: Masahito Kawabata
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Patent number: 8054646Abstract: The present invention provides a circuit board connecting structure enabled to obtain the reliable connection between circuit patterns by restricting the elongation of a flexible base material even when connecting portions are arranged in a face-to-face configuration and are press-contacted with each other. A circuit board connecting structure 10 includes a first circuit board 11, and a second circuit board 12. The circuit board connecting structure 10 is configured so that when a first connecting portion 13 and a second connecting portion 14 are sandwiched by a pair of pressing jigs 18, 19 and are press-contacted with each other, one 23 of first outer dummy terminals is accommodated between columns of ones 33, 33 of second outer dummy terminals, while the other first outer dummy terminal 24 is accommodated between columns of the other ones 34, 34 of the second outer dummy terminals.Type: GrantFiled: February 20, 2006Date of Patent: November 8, 2011Assignee: Panasonic CorporationInventors: Masahito Kawabata, Yoshihito Fujiwara
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Publication number: 20110249417Abstract: An anisotropic conductive resin includes a thermosetting resin and an alloy. A relationship of T1<T3<T2<T4 is satisfied, where T1 is a reaction start temperature of the thermosetting resin, T2 is a reaction peak temperature of the thermosetting resin, T3 is a solidus temperature of the alloy, and T4 is a liquidus temperature of the alloy.Type: ApplicationFiled: July 15, 2009Publication date: October 13, 2011Applicant: PANASONIC CORPORATIONInventor: Masahito Kawabata
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Patent number: 8018737Abstract: The invention provides a connecting structure of a circuit board, a connecting part of the circuit board, and an electronic device capable of alleviating a temperature difference between the connecting parts under hot pressure welding. A connecting structure 10 of a circuit board comprises a first circuit board 11 and a second circuit board 12, with a first connecting part 15 and a second connecting part 16 opposedly disposed via an adhesive 13. The first connecting part 15 and the second connecting part 16 are pinched by a pair of pressurizing jigs 20 and subjected to hot pressure welding so that first circuit patterns 17 and second circuit patterns 18 are in contact with each other.Type: GrantFiled: December 22, 2005Date of Patent: September 13, 2011Assignee: Panasonic CorporationInventors: Yoshihito Fujiwara, Masahito Kawabata
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Publication number: 20110199735Abstract: There is provided a substrate connecting structure capable of preventing occurrence of a connection failure, which would otherwise be caused by a non-uniform temperature rise within a connecting areas of circuit boards during thermocompression bonding.Type: ApplicationFiled: February 22, 2010Publication date: August 18, 2011Applicant: PANASONIC CORPORATIONInventor: Masahito Kawabata
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Patent number: 7999376Abstract: An object of the present invention is to provide a semiconductor device by packaging a plurality of semiconductor chips three-dimensionally in a smaller thickness, with a smaller footprint, at the lower cost without using any other components and through a simpler manufacturing process of the semiconductor device than with the conventional methods. A flip chip packaging structure is formed by directly connecting a first semiconductor chip (101) reduced in thickness by back grinding and a substrate (105) via a bump electrode (102) to a wiring pattern (106). Also, a second semiconductor chip (103) is formed with an electrode (104) that is higher than the sum of the thickness of the first semiconductor chip (101) and the height of the electrode (102), and the electrode (104) is directly connected to the wiring pattern (106) on the substrate (105), whereby the most-compact three-dimensional semiconductor packaged device is produced.Type: GrantFiled: January 25, 2006Date of Patent: August 16, 2011Assignee: Panasonic CorporationInventors: Masahito Kawabata, Yoshihito Fujiwara
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Publication number: 20090178837Abstract: The present invention provides a circuit board connecting structure enabled to obtain the reliable connection between circuit patterns by restricting the elongation of a flexible base material even when connecting portions are arranged in a face-to-face configuration and are press-contacted with each other. A circuit board connecting structure 10 includes a first circuit board 11, and a second circuit board 12. The circuit board connecting structure 10 is configured so that when a first connecting portion 13 and a second connecting portion 14 are sandwiched by a pair of pressing jigs 18, 19 and are press-contacted with each other, one 23 of first outer dummy terminals is accommodated between columns of ones 33, 33 of second outer dummy terminals, while the other first outer dummy terminal 24 is accommodated between columns of the other ones 34, 34 of the second outer dummy terminals.Type: ApplicationFiled: February 20, 2006Publication date: July 16, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masahito Kawabata, Yoshihito Fujiwara
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Publication number: 20090176384Abstract: The invention provides a connecting structure of a circuit board, a connecting part of the circuit board, and an electronic device capable of alleviating a temperature difference between the connecting parts under hot pressure welding. A connecting structure 10 of a circuit board comprises a first circuit board 11 and a second circuit board 12, with a first connecting part 15 and a second connecting part 16 opposedly disposed via an adhesive 13. The first connecting part 15 and the second connecting part 16 are pinched by a pair of pressurizing jigs 20 and subjected to hot pressure welding so that first circuit patterns 17 and second circuit patterns 18 are in contact with each other.Type: ApplicationFiled: December 22, 2005Publication date: July 9, 2009Applicant: PANASONIC CORPORATIONInventors: Yoshihito Fujiwara, Masahito Kawabata
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Publication number: 20080265436Abstract: An object of the present invention is to provide a semiconductor device by packaging a plurality of semiconductor chips three-dimensionally in a smaller thickness, with a smaller footprint, at the lower cost without using any other components and through a simpler manufacturing process of the semiconductor device than with the conventional methods. A flip chip packaging structure is formed by directly connecting a first semiconductor chip (101) reduced in thickness by back grinding and a substrate (105) via a bump electrode (102) to a wiring pattern (106). Also, a second semiconductor chip (103) is formed with an electrode (104) that is higher than the sum of the thickness of the first semiconductor chip (101) and the height of the electrode (102), and the electrode (104) is directly connected to the wiring pattern (106) on the substrate (105), whereby the most-compact three-dimensional semiconductor packaged device is produced.Type: ApplicationFiled: January 25, 2006Publication date: October 30, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masahito Kawabata, Yoshihito Fujiwara