Patents by Inventor Masahito Kodama
Masahito Kodama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240132253Abstract: The present invention provides a sheet material container being made of a sheet material and including a body portion and a bottom portion that is to be disposed on a placement surface, and the sheet material including a plurality of film layers. A body portion sheet that constitutes the body portion includes a bonding portion where peripheral edge portions of the sheet materials are bonded. In a bottom surface sheet that constitutes the bottom portion, a non-adhesive region is provided in the plurality of film layers. The non-adhesive region forms a bottom filler-filled portion. The bottom filler-filled portion extends annularly around a non-filled portion, and includes at least three protruding leg portions that are to be placed on the placement surface so as to allow the container to stand by itself. The protruding leg portions protrude toward the placement surface past other portions in the bottom filler-filled portion due a leg forming portion.Type: ApplicationFiled: December 11, 2023Publication date: April 25, 2024Applicant: Kao CorporationInventors: Yoshinori INAGAWA, Mitsugu IWATSUBO, Takahiro OTSUKA, Masahito CHIWAKI, Daisuke KODAMA
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Patent number: 10381469Abstract: A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.Type: GrantFiled: August 28, 2014Date of Patent: August 13, 2019Assignee: DENSO CORPORATIONInventors: Yoshinori Tsuchiya, Shinichi Hoshi, Kazuyoshi Tomita, Kenji Itoh, Masahito Kodama, Tsutomu Uesugi
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Publication number: 20160372587Abstract: A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.Type: ApplicationFiled: August 28, 2014Publication date: December 22, 2016Inventors: Yoshinori TSUCHIYA, Shinichi HOSHI, Kazuyoshi TOMITA, Kenji ITOH, Masahito KODAMA, Tsutomu UESUGI
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Publication number: 20110316049Abstract: Provided are a vertical nitride semiconductor device in which occurrence of leak currents can be suppressed, and a method for manufacturing such nitride semiconductor device. A nitride semiconductor device, which is a vertical HEMT, is provided with an n? type GaN first nitride semiconductor layer, p+ type GaN second nitride semiconductor layers, an n? type GaN third nitride semiconductor layer, and an n? type AlGaN fourth nitride semiconductor layer that is in hetero junction with a front surface of the third nitride semiconductor layer. Openings that penetrate the third nitride semiconductor layer and reach front surfaces of the second nitride semiconductor layers are provided at positions isolated from the peripheral edge of the third nitride semiconductor layer. Source electrodes are provided in the openings. Etching damage that is in contact with the source electrodes is surrounded by a region where no etching damage is formed.Type: ApplicationFiled: March 2, 2009Publication date: December 29, 2011Applicants: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Narumasa Soejima, Tsutomu Uesugi, Masahito Kodama, Eiko Ishii
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Patent number: 7696071Abstract: The invention provides a method for producing a group III nitride based semiconductor having a reduced number of crystal defects. A GaN layer 2 is epitaxially grown on a sapphire substrate 1 having C-plane as a main plane (FIG. 1A). Then, the layer is wet-etched by use of a 25% aqueous TMAH solution at 85° C. for one hour, to thereby form an etch pit 4 (FIG. 1B). Then, a GaN layer 5 is grown on the GaN layer 2 through the ELO method (FIG. 1C). The thus-formed GaN layer 5 has a screw dislocation density lower than that of the GaN layer 2.Type: GrantFiled: October 24, 2007Date of Patent: April 13, 2010Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyota Jidosha Kabushiki KaishaInventors: Masahito Kodama, Eiko Hayashi, Masahiro Sugimoto
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Publication number: 20080142845Abstract: A HEMT has a drain region adapted to be electrically connected to a high voltage of an electric source, a source region adapted to be electrically connected to a low voltage of the electric source. A first semiconductor region is disposed between the drain region and the source region. A MIS structure and a heterostructure are disposed at a surface of the first semiconductor region. The MIS structure includes a gate electrode that faces a portion of a surface of the first semiconductor region with a gate insulating membrane therebetween. The heterostructure includes a second semiconductor region which makes contact with a rest portion of the surface of the first semiconductor region and has a wider band-gap than the first semiconductor region. The drain region and the source region are capable of being electrically connected with a structure in which the MIS structure 40 and the heterostructure are arranged in series.Type: ApplicationFiled: December 13, 2007Publication date: June 19, 2008Inventors: Masahito KODAMA, Eiko HAYASHI, Tsutomu UESUGI, Masahiro SUGIMOTO
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Publication number: 20080105954Abstract: A group III nitride based semiconductor device which has a trench or mesa structure and of which leakage of current and reduction of breakdown voltage are prevented. A GaN layer 2 was grown on a C-plane sapphire substrate 1, and a T-shaped USG film 3 was formed on the GaN layer 2 so that side surfaces of the USG film 3 were arranged parallel to A-plane and M-plane of the GaN layer 2. Thereafter, by using the USG film 3 as a mask, the GaN layer 2 was dry-etched. As is clear from FIGS. 2A and 2B, the M-plane is less roughened as compared with the A-plane. Subsequently, wet-etched was performed by use of an aqueous TMAH solution. As is clear from FIGS. 2C and 2D, roughness of the A-plane and the M-plane are removed, and, particularly, the M-plane assumes a mirror surface. Thus, through provision of M-plane side surfaces of a trench or an etching-formed mesa, leakage of current and reduction of breakdown voltage of a group III nitride based semiconductor device can be prevented.Type: ApplicationFiled: October 24, 2007Publication date: May 8, 2008Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masahito KODAMA, Eiko HAYASHI, Masahiro SUGIMOTO
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Publication number: 20080105903Abstract: The invention provides a method for producing a group III nitride based semiconductor having a reduced number of crystal defects. A GaN layer 2 is epitaxially grown on a sapphire substrate 1 having C-plane as a main plane (FIG. 1A). Then, the layer is wet-etched by use of a 25% aqueous TMAH solution at 85° C. for one hour, to thereby form an etch pit 4 (FIG. 1B) Then, a GaN layer 5 is grown on the GaN layer 2 through the ELO method (FIG. 1C). The thus-formed GaN layer 5 has a screw dislocation density lower than that of the GaN layer 2.Type: ApplicationFiled: October 24, 2007Publication date: May 8, 2008Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masahito KODAMA, Eiko HAYSASHI, Masahiro SUGIMOTO
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Patent number: 6844246Abstract: A GaN layer 32 grows in vertical direction on a GaN layer 31 where neither a first mask 41m nor a second mask 42m is formed. When thickness of the GaN layer 32 becomes larger than that of the first mask 41m, it began to grown in lateral direction so as to cover the first mask 41m. Because the second mask 42m is not formed on the upper portion of the first mask 41m, the GaN layer 32 grows in vertical direction. On the contrary, at the upper region of the GaN layer 31 where the mask 41m is not formed, the second mask 42m is formed like eaves, the growth of the GaN layer 32 stops and threading dislocations propagated with vertical growth also stops there. The GaN layer 32 grows in vertical direction so as to penetrate the region where neither the first mask 41m nor the second mask 42m is formed. When the height of the GaN layer 32 becomes larger than that of the second mask 42m, the GaN layer 32 begins to grow in lateral direction again and covers the second mask 42m.Type: GrantFiled: March 19, 2002Date of Patent: January 18, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Seiji Nagai, Kazuyoshi Tomita, Masahito Kodama
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Publication number: 20040087115Abstract: A GaN layer 32 grows in vertical direction on a GaN layer 31 where neither a first mask 41m nor a second mask 42m is formed. When thickness of the GaN layer 32 becomes larger than that of the first mask 41m, it began to grown in lateral direction so as to cover the first mask 41m. Because the second mask 42m is not formed on the upper portion of the first mask 41m, the GaN layer 32 grows in vertical direction. On the contrary, at the upper region of the GaN layer 31 where the mask 41m is not formed, the second mask 42m is formed like eaves, the growth of the GaN layer 32 stops and threading dislocations propagated with vertical growth also stops there. The GaN layer 32 grows in vertical direction so as to penetrate the region where neither the first mask 41m nor the second mask 42m is formed. When the height of the GaN layer 32 becomes larger than that of the second mask 42m, the GaN layer 32 begins to grow in lateral direction again and covers the second mask 42m.Type: ApplicationFiled: November 5, 2003Publication date: May 6, 2004Inventors: Seiji Nagai, Kazuyoshi Tomita, Masahito Kodama
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Patent number: 6700175Abstract: There is provided a method of manufacturing a vertical semiconductor device including a structural section in which an n−-type semiconductor region and a p−-type semiconductor region are arranged alternately without filling trenches by epitaxial growth. A p−-type silicon layer (13) which becomes a p−-type semiconductor region (12) is formed. An n−-type semiconductor region (11) is formed by diffusing n-type impurities into the p−-type silicon layer (13) through the sidewalls of first trenches (22) formed in the p−-type silicon layer (13).Type: GrantFiled: December 31, 2001Date of Patent: March 2, 2004Assignee: Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Masahito Kodama, Tsutomu Uesugi
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Patent number: 6072215Abstract: Disclosed is a semiconductor device including a lateral MOS element which comprises a p-type silicon substrate; a first semiconductor layer of an n-type constituting a drift region; a second semiconductor layer of the p-type selectively provided in the first semiconductor layer, and constituting a body region, in which a channel region is partially formed; a third semiconductor layer of the n-type selectively provided in a surface of the second semiconductor layer, and constituting a source region; a fourth semiconductor layer of the n-type provided in the first semiconductor layer, and constituting a drain region; and a trench gate. The trench gate is constructed such that a trench formed in the first semiconductor layer is filled with a gate electrode with an insulating film interposed therebetween. The trench gate is formed such that at least a bottom thereof is in contact with the semiconductor substrate.Type: GrantFiled: March 25, 1999Date of Patent: June 6, 2000Assignee: Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Sachiko Kawaji, Masahito Kodama, Takashi Suzuki, Tsutomu Uesugi
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Patent number: 5708286Abstract: A vertical semiconductor device having an insulated gate structure makes use of a double-gate structure. The double-gate structure dramatically reduces the channel resistance, JFET resistance, and epitaxial resistance of the on-resistance of the power MOSFET, and implements an adequate breakdown voltage due to the effect of gate bias. In principle, a first gate and second gate having mutually facing portions are driven synchronously. This causes first and second channels to be formed in correspondence with first and second gates, and the currents flowing through these first and second channels form the on-current for this power device having a vertical structure.Type: GrantFiled: March 29, 1996Date of Patent: January 13, 1998Assignee: Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Tsutomu Uesugi, Masahito Kodama