Abstract: An elapsed cycle number during the predetermined period of the inputted clock source is counted using the clock reference signal as a yardstick, a frequency of the clock source is computed based on an elapsed cycle number obtained by counting, control timing of various interfaces relating to the CPU is adjusted and an interruption generating interval in which interruption is generated regularly by the CPU so that adjustment of control timing of various interfaces and setting of a timer interruption interval during the OS operation in accordance with a frequency of the clock source without performing OS modification such as rebuilding and the like.

Abstract: An elapsed cycle number during the predetermined period of the inputted clock source is counted using the clock reference signal as a yardstick, a frequency of the clock source is computed based on an elapsed cycle number obtained by counting, control timing of various interfaces relating to the CPU is adjusted and an interruption generating interval in which interruption is generated regularly by the CPU so that adjustment of control timing of various interfaces and setting of a timer interruption interval during the OS operation in accordance with a frequency of the clock source without performing OS modification such as rebuilding and the like.

Abstract: In the initialization of a multiprocessor system, device history information containing mounting position information indicating a mounting position of a CPU board supplied from a history information supplying unit is stored in a nonvolatile storage unit in the CPU board capable of storing plural pieces of device history information, so that the mounting position information on each of CPU boards can be accurately and automatically recorded in each CPU board and the history of the mounting position of the CPU board can be recorded and managed on a CPU board by CPU board basis.

Abstract: In a multi-processor system, each processor transmits a system time synchronous signal to another processor using hardware, and measures the propagation delay time of the signal. Then, the timer value of each processor is adjusted with the measured propagation delay time.

Abstract: A microprocessor is equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The microprocessor includes a large-capacity low-associativity address translation buffer, and is capable of avoiding limitations imposed on a TLB entry lock function, while reducing the overhead for address translation. The address translation mechanism comprises an address translation buffer having an entry lock function, and control logic for controlling the operation of the address translation buffer. The address translation buffer includes a lower-level buffer organized as a lower-level hierarchy of the address translation buffer and having no entry lock function, and a higher-level buffer organized as a higher-level hierarchy of the address translation buffer and having an entry lock function, the higher-level buffer having higher associativity than the associativity of the lower-level buffer.

Abstract: In a multi-processor system, each processor transmits a system time synchronous signal to another processor using hardware, and measures the propagation delay time of the signal. Then, the timer value of each processor is adjusted with the measured propagation delay time.

Abstract: A condition code producing system for an arithmetic unit which is controlled by a micro program and operate on binary floating point data produces a condition code having a plurality of bits and describing an attribute of the binary floating point data. The condition code producing system comprises: a storing device for storing each bit of the condition code; a device for producing a plurality of detection signals from values of predetermined bits of the binary floating point data. This data is transferred to a bus within the arithmetic unit by a micro instruction which involves a data transfer, where the micro instruction is one of a plurality of micro instructions constituting the micro program. The micro instruction comprises a condition control field constituted by a plurality of bits having values depending on at least precision and data portions of the binary floating point data which is transferred.