Abstract: A matrix switch is provided with a plurality of input-terminals, a plurality of output-terminals, a plurality of connector switch elements connecting the plurality of input-terminals with the plurality of output-terminals, a plurality of input-terminal shunts associated with the plurality of input-terminals, and a plurality of output-terminal shunts associated with the plurality of output-terminals. Each input-terminal is connected to at least any one of the plurality of input-terminal shunts, and the input-terminal shunt connects the associated input-terminal to a predetermined impedance load as necessary. Each output-terminal is connected to at least any one of the plurality of output-terminal shunts, and the output-terminal shunt terminates the associated output-terminal in a predetermined impedance as necessary.

Abstract: A matrix switch is provided with a plurality of input-terminals, a plurality of output-terminals, a plurality of connector switch elements connecting the plurality of input-terminals with the plurality of output-terminals, a plurality of input-terminal shunts associated with the plurality of input-terminals, and a plurality of output-terminal shunts associated with the plurality of output-terminals. Each input-terminal is connected to at least any one of the plurality of input-terminal shunts, and the input-terminal shunt connects the associated input-terminal to a predetermined impedance load as necessary. Each output-terminal is connected to at least any one of the plurality of output-terminal shunts, and the output-terminal shunt terminates the associated output-terminal in a predetermined impedance as necessary.

Abstract: A void-collection section is provided on a GaAs FET chip at a location that avoids a heat-generating region of the chip. Pressure is applied to the rear surface of the substrate corresponding to the heat-generating region of the chip, this causing the removal of a void from immediately under the heat-generating section, and the capture of the void by the void-collection section, thereby suppressing the localized rise in temperature of the chip caused by the existence of the void.