Abstract: An instruction decoding device for a data processor which is capable of predicting a branch address is disclosed. A program counter value calculation device can be used to calculate the branch target address. An address calculation device can be used to calculate an operand address. The address calculation device can calculate the operand address by adding the instruction length of the branch instruction and the program counter value of the branch instruction. In this way the apparatus performs branching processing for the unconditional branch instructions, conditional branch instructions, subroutine branch instructions and loop control instructions at the instruction decoding stage to suppress disturbances in the pipeline processing.

Abstract: A data processor which includes a pipeline processing unit that processes instructions, including a POP instruction. The POP instruction includes a destination operand field and has a stack top as a source. The destination for the POP instruction can be register or a memory location. The pipeline processing unit is capable of performing pre-processing with respect to both the source and destination operands prior to execution by an execution stage of the pipeline processing unit. When the destination is a memory location, pre-processing of the destination uses information from the destination operand field. When the destination operand is a general register, steps for pre-processing of the destination are merged prior to the execution stage. Pre-processing of the source uses information from the stackpointer and is conducted prior to the execution phase in response to the decoding of the operation code field of the POP instruction.

Abstract: The data processor of this invention is provided with a multi-stage pipeline processing mechanism which predicts the probability of the branch instruction branching at the instruction decoding stage. The mechanism also detects exceptions at pre-branching and transmits information about a detected exception to the instruction execution stage. If, at the execution stage, it is determined that the branch prediction was incorrect, exception processing is not started. If, at the execution stage, it is determined that the branch prediction was correct, exception processing is started. In this way it is possible to reduce disturbances in pipeline processing for many branch instructions.

Abstract: A data processor which is so constructed that an operation code decoder decodes an operation code in an instruction to be processed comprising an operation code and an operand descriptor, and an addressing mode decoder decodes the operand descriptor, so that when the addressing mode of the operand is detected to be a specified addressing mode, for example, a register direct addressing mode, an entry address of microinstruction generated by the operation code decoder is modified, thereby enabling the entry address, different in microinstruction during the specified addressing mode and others, to be generated without increasing the number of product terms of a PLA in an instruction decoder.