Patents by Inventor Masahito Numanami

Masahito Numanami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11264952
    Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 1, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Tetsuaki Adachi, Kazuo Watanabe, Masahito Numanami, Yasuhisa Yamamoto
  • Patent number: 10965325
    Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 30, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Tetsuaki Adachi, Masahito Numanami, Yasuhisa Yamamoto
  • Patent number: 10944438
    Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 9, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Tetsuaki Adachi, Masahito Numanami, Yasuhisa Yamamoto
  • Publication number: 20210006205
    Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Inventors: Satoshi TANAKA, Tetsuaki ADACHI, Kazuo WATANABE, Masahito NUMANAMI, Yasuhisa YAMAMOTO
  • Patent number: 10819286
    Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 27, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Tetsuaki Adachi, Kazuo Watanabe, Masahito Numanami, Yasuhisa Yamamoto
  • Publication number: 20190190546
    Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Inventors: Satoshi TANAKA, Kazuo WATANABE, Tetsuaki ADACHI, Masahito NUMANAMI, Yasuhisa YAMAMOTO
  • Publication number: 20190190547
    Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Inventors: Satoshi TANAKA, Kazuo WATANABE, Tetsuaki ADACHI, Masahito NUMANAMI, Yasuhisa YAMAMOTO
  • Patent number: 10256848
    Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: April 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Tetsuaki Adachi, Masahito Numanami, Yasuhisa Yamamoto
  • Patent number: 10256849
    Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: April 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Tetsuaki Adachi, Masahito Numanami, Yasuhisa Yamamoto
  • Publication number: 20190103841
    Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventors: Satoshi TANAKA, Tetsuaki ADACHI, Kazuo WATANABE, Masahito NUMANAMI, Yasuhisa YAMAMOTO
  • Patent number: 10171036
    Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: January 1, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Tetsuaki Adachi, Kazuo Watanabe, Masahito Numanami, Yasuhisa Yamamoto
  • Publication number: 20180062579
    Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.
    Type: Application
    Filed: July 21, 2017
    Publication date: March 1, 2018
    Inventors: Satoshi Tanaka, Tetsuaki Adachi, Kazuo Watanabe, Masahito Numanami, Yasuhisa Yamamoto
  • Publication number: 20180006608
    Abstract: Provided is a bias circuit that supplies a first bias current or voltage to an amplifier that amplifies a radio frequency signal. The bias circuit includes: an FET that has a power supply voltage supplied to a drain thereof and that outputs the first bias current or voltage from a source thereof; a first bipolar transistor that has a collector thereof connected to a gate of the FET, that has a base thereof connected to the source of the FET, that has a common emitter and that has a constant current supplied to the collector thereof; and a first capacitor that has one end thereof connected to the collector of the first bipolar transistor and that suppresses variations in a collector voltage of the first bipolar transistor.
    Type: Application
    Filed: April 6, 2017
    Publication date: January 4, 2018
    Inventors: Satoshi TANAKA, Tetsuaki ADACHI, Kazuo WATANABE, Masahito NUMANAMI, Yasuhisa YAMAMOTO
  • Publication number: 20170302300
    Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.
    Type: Application
    Filed: April 18, 2017
    Publication date: October 19, 2017
    Inventors: Satoshi TANAKA, Kazuo WATANABE, Tetsuaki ADACHI, Masahito NUMANAMI, Yasuhisa YAMAMOTO
  • Publication number: 20170302301
    Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.
    Type: Application
    Filed: April 18, 2017
    Publication date: October 19, 2017
    Inventors: Satoshi TANAKA, Kazuo WATANABE, Tetsuaki ADACHI, Masahito NUMANAMI, Yasuhisa YAMAMOTO
  • Patent number: 7868699
    Abstract: The present invention is to provide a technique which optimizes a gate resistor of a bias circuit to thereby make it possible to greatly improve a distortion characteristic of a power amplifier. A bias circuit used as for biasing the gate of a final-stage power transistor is included in a power amplifier provided in a communication mobile system. In the bias circuit, an inductance and a resistor are series-connected between a power supply voltage and the gate of the power transistor. The resistance value of the resistor is set to approximately the same order as an input impedance of the power transistor. When the input impedance of the power transistor is about 10? or so, for example, the resistor is set to about a few ? to about 100?. Thus, the gain of the power transistor at a low-frequency band can greatly be suppressed.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: January 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hideyuki Ono, Toru Fujioka, Masahito Numanami
  • Publication number: 20080287090
    Abstract: The present invention is to provide a technique which optimizes a gate resistor of a bias circuit to thereby make it possible to greatly improve a distortion characteristic of a power amplifier. A bias circuit used as for biasing the gate of a final-stage power transistor is included in a power amplifier provided in a communication mobile system. In the bias circuit, an inductance and a resistor are series-connected between a power supply voltage and the gate of the power transistor. The resistance value of the resistor is set to approximately the same order as an input impedance of the power transistor. When the input impedance of the power transistor is about 10? or so, for example, the resistor is set to about a few ? to about 100?. Thus, the gain of the power transistor at a low-frequency band can greatly be suppressed.
    Type: Application
    Filed: July 25, 2008
    Publication date: November 20, 2008
    Inventors: Hideyuki Ono, Toru Fujioka, Masahito Numanami
  • Patent number: 7411457
    Abstract: The present invention is to provide a technique which optimizes a gate resistor of a bias circuit to thereby make it possible to greatly improve a distortion characteristic of a power amplifier. A bias circuit used as for biasing the gate of a final-stage power transistor is included in a power amplifier provided in a communication mobile system. In the bias circuit, an inductance and a resistor are series-connected between a power supply voltage and the gate of the power transistor. The resistance value of the resistor is set to approximately the same order as an input impedance of the power transistor. When the input impedance of the power transistor is about 10? or so, for example, the resistor is set to about a few ? to about 100?. Thus, the gain of the power transistor at a low-frequency band can greatly be suppressed.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: August 12, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hideyuki Ono, Toru Fujioka, Masahito Numanami
  • Patent number: 7145394
    Abstract: A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: December 5, 2006
    Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Masahito Numanami, Hitoshi Akamine, Tsuyoshi Shibuya, Tetsuaki Adachi, Masatoshi Morikawa, Yasuhiro Nunogawa
  • Publication number: 20060255861
    Abstract: The present invention is to provide a technique which optimizes a gate resistor of a bias circuit to thereby make it possible to greatly improve a distortion characteristic of a power amplifier. A bias circuit used as for biasing the gate of a final-stage power transistor is included in a power amplifier provided in a communication mobile system. In the bias circuit, an inductance and a resistor are series-connected between a power supply voltage and the gate of the power transistor. The resistance value of the resistor is set to approximately the same order as an input impedance of the power transistor. When the input impedance of the power transistor is about 10 ? or so, for example, the resistor is set to about a few ? to about 100 ?. Thus, the gain of the power transistor at a low-frequency band can greatly be suppressed.
    Type: Application
    Filed: May 11, 2006
    Publication date: November 16, 2006
    Inventors: Hideyuki Ono, Toru Fujioka, Masahito Numanami