Patents by Inventor Masahito Sugiura
Masahito Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140242085Abstract: As a result of the analysis by an SST-REX method so as to identify a target molecule for treating and testing an Aspergillus fumigatus infection, a YMAF1 protein has been found out, which is mainly localized in the cell wall of Aspergillus fumigatus. Moreover, it has been found out that YMAF1 protein-deficient Aspergillus fumigatus has reduced spore-forming ability and pathogenicity. Further, it has been found out that the survival rate of experimental mice having aspergillosis (invasive Aspergillus model mice) is improved by preparing and administering an antibody against the YMAF1 protein. Furthermore, it has been found out that Aspergillus fumigatus can be detected with a favorable sensitivity by an ELISA system using the antibody.Type: ApplicationFiled: August 12, 2011Publication date: August 28, 2014Applicants: MEDICAL & BIOLOGICAL LABORATORIES CO., LTD., NATIONAL INSTITUTE OF INFECTIOUS DISEASESInventors: Yoshitsugu Miyazaki, Satoshi Yamagoe, Masunori Kajikawa, Masahito Sugiura, Reiko Itoh, Hirotaka Kumagai
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Publication number: 20130121914Abstract: The present invention provides an agent for the prophylaxis or therapy of autoimmune diseases or allergic diseases, which contains an anti-Embigin antibody, particularly an anti-Embigin antibody showing cytotoxicity or a cytotoxicity inducing activity, an agent for the prophylaxis or therapy of diseases involving Th17 cell, and a cytotoxic agent to Th17 cell. In addition, an agent for detection of Th17 cell, which contains an anti-Embigin antibody, a convenient detection method of Th17 cell, which uses the agent, a method of efficiently delivering a drug and the like in a Th17 cell selective manner, which uses an anti-Embigin antibody, and a drug delivery system to Th17 cell are provided.Type: ApplicationFiled: June 2, 2011Publication date: May 16, 2013Applicant: DAINIPPON SUMITOMO PHARMA CO., LTD.Inventors: Koichi Kino, Toshihiro Kai, Mitsuhiro Matsumoto, Masunori Kajikawa, Masahito Sugiura, Emi Shimizu
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Publication number: 20120107364Abstract: By utilizing an SST-REX method, a cDNA encoding a protein expressed on a cell surface or secreted from the cell was selected from a cDNA library derived from a cancer cell line. Monoclonal antibodies against the protein encoding the selected cDNA were prepared. The in vitro and in vivo anti-cancer activities and binding to various cancer cells lines were examined. As a result, a monoclonal antibody which binds to a PODXL2 protein, and which had excellent anti-cancer activities was found. Further, a region including an epitope of the antibody was successfully identified, and the amino acid sequences of variable regions of a light chain and a heavy chain were successfully determined.Type: ApplicationFiled: July 7, 2010Publication date: May 3, 2012Applicant: ACTGEN INC.Inventors: Masunori Kajikawa, Masahito Sugiura, Kazuyuki Atarashi, Emi Shimizu, Chiemi Matsumi, Yukie Saitoh
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Patent number: 8168539Abstract: A tungsten film with a lower specific resistance and a lower fluorine concentration over its boundary with the base barrier layer, which adheres to the barrier layer with a high level of reliability, compared to tungsten films formed through methods in the related art, is formed. The tungsten film is formed through a process in which a silicon-containing gas is delivered to a wafer M placed within a processing container 14 and a process executed after the silicon-containing gas supply process, in which a first tungsten film 70 is formed by alternately executing multiple times, a tungsten-containing gas supply step for supplying a tungsten-containing gas and a hydrogen compound gas supply step for supplying a hydrogen compound gas with no silicon content with a purge step in which an inert gas is supplied into the processing container and/or an evacuation step for evacuating the processing container executed between the tungsten-containing gas supply step and the hydrogen compound gas supply step.Type: GrantFiled: June 23, 2006Date of Patent: May 1, 2012Assignee: Tokyo Electron LimitedInventors: Masahito Sugiura, Yasutaka Mizoguchi, Yasushi Aiba
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Publication number: 20090246373Abstract: A metal film with a lowered resistance by controlling a crystal structure. A tungsten film is formed through a first tungsten film formation in which a first tungsten film with amorphous content is formed by alternately executing multiple times a supplying a metal base material gas such as WF6 gas and supplying a hydrogen compound gas such as SiH4 gas, with a purge executed between the two gas supply by supplying an inert gas such as Ar gas or N2 gas and a second tungsten film formation in which a second tungsten film is formed by simultaneously supplying the WF6 gas and a reducing gas such as H2 gas onto the first tungsten film. The amorphous content in the first tungsten film is controlled by adjusting the length of time over which the purge is executed following the SiH4 gas supply.Type: ApplicationFiled: July 6, 2006Publication date: October 1, 2009Applicant: Tokyo Electron LimitedInventors: Mitsuhiro Tachibana, Masahito Sugiura, Takashi Nishimori, Kohichi Satoh
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Publication number: 20090045517Abstract: A tungsten film with a lower specific resistance and a lower fluorine concentration over its boundary with the base barrier layer, which adheres to the barrier layer with a high level of reliability, compared to tungsten films formed through methods in the related art, is formed. The tungsten film is formed through a process in which a silicon-containing gas is delivered to a wafer M placed within a processing container 14 and a process executed after the silicon-containing gas supply process, in which a first tungsten film 70 is formed by alternately executing multiple times, a tungsten-containing gas supply step for supplying a tungsten-containing gas and a hydrogen compound gas supply step for supplying a hydrogen compound gas with no silicon content with a purge step in which an inert gas is supplied into the processing container and/or an evacuation step for evacuating the processing container executed between the tungsten-containing gas supply step and the hydrogen compound gas supply step.Type: ApplicationFiled: June 23, 2006Publication date: February 19, 2009Applicant: Tokyo Electron LimitedInventors: Masahito Sugiura, Yasutaka Mizoguchi, Yasushi Aiba
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Patent number: 7078341Abstract: A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process. The TCVD process utilizes high flow rate of a dilute process gas containing a metal-carbonyl precursor to deposit a metal layer. In one embodiment of the invention, the metal-carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12. In another embodiment of the invention, a method is provided for depositing a W layer from a process gas comprising a W(CO)6 precursor at a substrate temperature of about 410° C. and a chamber pressure of about 200 mTorr.Type: GrantFiled: September 30, 2003Date of Patent: July 18, 2006Assignees: Tokyo Electron Limited, International Business Machines CorporationInventors: Hideaki Yamasaki, Tsukasa Matsuda, Atsushi Gomi, Tatsuo Hatano, Masahito Sugiura, Yumiko Kawano, Gert J Leusink, Fenton R McFeely, Sandra G. Malhotra
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Patent number: 7037560Abstract: A film forming and film modifying method utilizing a film forming apparatus which has an alcohol supply unit to form a metal oxide film on a semiconductor wafer in a vacuum atmosphere in which a vaporized metal oxide film material and a vaporized alcohol exist. The film modifying method irradiates a UV ray on ozone to generate active oxygen atoms, thus modifying the metal oxide film by exposing the metal oxide film to the active oxygen atoms in a vacuum atmosphere.Type: GrantFiled: July 14, 2000Date of Patent: May 2, 2006Assignee: Tokyo Electron LimitedInventors: Hiroshi Shinriki, Masahito Sugiura
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Publication number: 20060081186Abstract: An insulating film consisting of first and second tantalum oxide layers is formed on a semiconductor wafer. First, an amorphous first layer is formed by CVD, and a reforming process for removing organic impurities contained in the first layer is carried out. Then, an amorphous second layer is formed by CVD on the first layer. Then, a reforming process for removing organic impurities contained in the second layer is carried out by supplying a process gas containing ozone into a process chamber while heating the wafer to a temperature lower than a crystallizing temperature over a certain period. Further, within the same process chamber, the wafer is successively heated to a second temperature higher than the crystallizing temperature, followed by cooling the wafer to a temperature lower than the crystallizing temperature so as to crystallize the first and second layers simultaneously.Type: ApplicationFiled: December 8, 2005Publication date: April 20, 2006Inventors: Hiroshi Shinriki, Masahito Sugiura
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Patent number: 7030028Abstract: A dual damascene structure with a lesser degree of shoulder loss is achieved. In a method for forming a dual damascene structure having a shoulder in an organic low k film layer by dry-etching the organic low k film layer 208 and a mask layer 210 formed over the organic low k film 208 using at least two different mixed gases, a first step in which the mask layer is etched using a first process gas and then the organic low k film layer is etched into a predetermined depth by continuously using the first process gas and a second step following the first step, in which the organic low k film layer is etched using a second process gas are executed. Since a protective wall is formed at a side wall of a via during the first step, the extent of the shoulder loss occurring in the junction region where a trench and a via form a junction can be reduced.Type: GrantFiled: June 26, 2001Date of Patent: April 18, 2006Assignees: Tokyo Electron Limited, NEC CorporationInventors: Takuya Mori, Koichiro Inazawa, Noriyuki Kobayashi, Masahito Sugiura, Yoshihiro Hayashi, Keizo Kinoshita
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Patent number: 6989321Abstract: A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process includes introducing a process gas containing a metal carbonyl precursor in a process chamber and depositing a metal layer on a substrate. The TCVD process utilizes a short residence time for the gaseous species in the processing zone above the substrate to form a low-resistivity metal layer. In one embodiment of the invention, the metal carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12 precursors. In another embodiment of the invention, a method is provided for depositing low-resistivity W layers at substrate temperatures below about 500° C., by utilizing a residence time less than about 120 msec.Type: GrantFiled: September 30, 2003Date of Patent: January 24, 2006Assignees: Tokyo Electron Limited, International Business Machines CorporationInventors: Hideaki Yamasaki, Tsukasa Matsuda, Atsushi Gomi, Tatsuo Hatano, Masahito Sugiura, Yumiko Kawano, Gert J Leusink, Fenton R McFeely, Sandra G. Malhotra
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Patent number: 6890848Abstract: A method of fabricating a semiconductor device includes the steps of forming a first insulation film on a substrate by a spin-on process, applying a curing process to the first insulation film at a temperature of 380-500° C. over a duration of 5-180 seconds, and forming a second insulation film on the first insulation film by a spin-on process.Type: GrantFiled: June 28, 2001Date of Patent: May 10, 2005Assignee: Tokyo Electron LimitedInventors: Kaoru Maekawa, Satohiko Hoshino, Masahito Sugiura, Federica Allegretti
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Publication number: 20050079708Abstract: A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process. The TCVD process utilizes high flow rate of a dilute process gas containing a metal-carbonyl precursor to deposit a metal layer. In one embodiment of the invention, the metal-carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12. In another embodiment of the invention, a method is provided for depositing a W layer from a process gas comprising a W(CO)6 precursor at a substrate temperature of about 410° C. and a chamber pressure of about 200 mTorr.Type: ApplicationFiled: September 30, 2003Publication date: April 14, 2005Applicants: Tokyo Electron Limited, International Business Machines CorporationInventors: Hideaki Yamasaki, Tsukasa Matsuda, Atsushi Gomi, Tatsuo Hatano, Masahito Sugiura, Yumiko Kawano, Gert Leusink, Fenton McFeely, Sandra Malhotra
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Publication number: 20050070100Abstract: A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process includes introducing a process gas containing a metal carbonyl precursor in a process chamber and depositing a metal layer on a substrate. The TCVD process utilizes a short residence time for the gaseous species in the processing zone above the substrate to form a low-resistivity metal layer. In one embodiment of the invention, the metal carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12 precursors. In another embodiment of the invention, a method is provided for depositing low-resistivity W layers at substrate temperatures below about 500° C., by utilizing a residence time less than about 120 msec.Type: ApplicationFiled: September 30, 2003Publication date: March 31, 2005Applicants: Tokyo Electron Limited, International Business Machines CorporationInventors: Hideaki Yamasaki, Tsukasa Matsuda, Atsushi Gomi, Tatsuo Hatano, Masahito Sugiura, Yumiko Kawano, Gert Leusink, Fenton McFeely, Sandra Malhotra
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Publication number: 20050026454Abstract: The present invention comprises the steps of performing a reforming process on a surface of a low dielectric constant insulation film formed on a substrate which includes one of a porous low dielectric constant insulation film and a non-porous low dielectric constant insulation film and forming an insulation film as at least one of an etching mask and a Chemical Mechanical Polishing stopper (CMP stopper) on the reformed surface of the low dielectric constant insulation film. For example, plasma is radiated as a reforming process mentioned above, the surface roughness of a low dielectric insulation film is increased and, as a result, adhesion between the films and also between the inter-layer insulation film and other neighboring films can be improved with so-called “anchor effect”.Type: ApplicationFiled: August 27, 2004Publication date: February 3, 2005Inventors: Nobuo Konishi, Mitsuaki Iwashita, Hiroki Ohno, Shigeru Kawamura, Masahito Sugiura
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Publication number: 20050016687Abstract: An insulating film consisting of first and second tantalum oxide layers is formed on a semiconductor wafer. First, an amorphous first layer is formed by CVD, and a reforming process for removing organic impurities contained in the first layer is carried out. Then, an amorphous second layer is formed by CVD on the first layer. Then, a reforming process for removing organic impurities contained in the second layer is carried out by supplying a process gas containing ozone into a process chamber while heating the wafer to a temperature lower than a crystallizing temperature over a certain period. Further, within the same process chamber, the wafer is successively heated to a second temperature higher than the crystallizing temperature, followed by cooling the wafer to a temperature lower than the crystallizing temperature so as to crystallize the first and second layers simultaneously.Type: ApplicationFiled: August 9, 2004Publication date: January 27, 2005Applicant: TOKYO ELECTRON LIMITEDInventors: Hiroshi Shinriki, Masahito Sugiura
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Publication number: 20040253777Abstract: A process gas constituted by a compound having a ring structure in its molecules is introduced into a chamber (12). In the meantime, an excitation gas such as argon, etc. is excited by an activator (34) and introduced into the chamber (12), so that the process gas is excited. The excited process gas is deposited on a process target substrate (19), forming a porous low dielectric constant film having ring structures in the film.Type: ApplicationFiled: February 27, 2004Publication date: December 16, 2004Inventors: Hidenori Miyoshi, Masahito Sugiura, Yusaku Kashiwagi, Yoshihisa Kagawa, Tomohiro Ohta
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Patent number: 6800546Abstract: The present invention comprises the steps of performing a reforming process on a surface of a low dielectric constant insulation film formed on a substrate which includes one of a porous low dielectric constant insulation film and a non-porous low dielectric constant insulation film and forming an insulation film as at least one of an etching mask and a Chemical Mechanical Polishing stopper (CMP stopper) on the reformed surface of the low dielectric constant insulation film. For example, plasma is radiated as a reforming process mentioned above, the surface roughness of a low dielectric insulation film is increased and, as a result, adhesion between the films and also between the inter-layer insulation film and other neighboring films can be improved with so-called “anchor effect”.Type: GrantFiled: March 12, 2002Date of Patent: October 5, 2004Assignee: Tokyo Electron LimitedInventors: Nobuo Konishi, Mitsuaki Iwashita, Hiroki Ohno, Shigeru Kawamura, Masahito Sugiura
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Publication number: 20040065957Abstract: A method of fabricating a semiconductor device includes the step of depositing a second insulating film on a first insulating film, patterning the second insulating film to form an opening therein, and etching the first insulating film while using the second insulating film as an etching mask, wherein a low-dielectric film is used for the second insulating film.Type: ApplicationFiled: April 21, 2003Publication date: April 8, 2004Inventors: Kaoru Maekawa, Masahito Sugiura
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Publication number: 20040063331Abstract: A dual damascene structure with a lesser degree of shoulder loss is achieved. In a method for forming a dual damascene structure having a shoulder in an organic low k film layer by dry-etching the organic low k film layer 208 and a mask layer 210 formed over the organic low k film 208 using at least two different mixed gases, a first step in which the mask layer is etched using a first process gas and then the organic low k film layer is etched into a predetermined depth by continuously using the first process gas and a second step following the first step, in which the organic low k film layer is etched using a second process gas are executed. Since a protective wall is formed at a side wall of a via during the first step, the extent of the shoulder loss occurring in the junction region where a trench and a via form a junction can be reduced.Type: ApplicationFiled: September 29, 2003Publication date: April 1, 2004Inventors: Takuya Mori, Koichiro Inazawa, Noriyuki Kobayashi, Masahito Sugiura, Yoshihiro Hayashi, Keizo Kinoshita