Abstract: An electro-optical device is an display device provided with a display region for displaying an image and a peripheral region provided outside the display region, and includes a first substrate including a plurality of pixel electrodes provided in the display region, a second substrate including a counter electrode facing the plurality of pixel s, a seal member being provided in the peripheral region, and containing a UV-curable material, and an electro-optical layer being arranged in a region surrounded by at the first substrate, the second substrate, and the seal member and having optical characteristics that change in accordance with an electric field, wherein one substrate of the first substrate and the second substrate includes a non-conductive region that overlaps with the seal member in plan view, is in the same layer as the plurality of pixel electrodes or the counter electrode, and is not provided with a film having conductivity.

Abstract: An electro-optical device is an display device provided with a display region for displaying an image and a peripheral region provided outside the display region, and includes a first substrate including a plurality of pixel electrodes provided in the display region, a second substrate including a counter electrode facing the plurality of pixel s, a seal member being provided in the peripheral region, and containing a UV-curable material, and an electro-optical layer being arranged in a region surrounded by at the first substrate, the second substrate, and the seal member and having optical characteristics that change in accordance with an electric field, wherein one substrate of the first substrate and the second substrate includes a non-conductive region that overlaps with the seal member in plan view, is in the same layer as the plurality of pixel electrodes or the counter electrode, and is not provided with a film having conductivity.

Abstract: Provided are a transistor, a pixel electrode provided corresponding to the transistor, a relay layer provided at a layer between the transistor and the pixel electrode and including, in this order from the pixel electrode side, a metal material layer containing a metal material, an insulating material layer containing an insulating material, and a metal material layer containing a metal material, and a lens layer provided at a layer between the relay layer and the pixel electrode and including a contact hole for electrically connecting the relay layer and the pixel electrode, and in the relay layer, portions of the metal material layer and the insulating material layer overlapping the contact hole are removed.

Abstract: A liquid crystal device includes a transistor, a pixel electrode provided corresponding to the transistor, a lens layer provided in a layer between the transistor and the pixel electrode, a relay layer provided in a layer between the transistor and the lens layer, and a contact plug configured to electrically connect the relay layer and the pixel electrode, and a part of the contact plug is provided in the relay layer.

Abstract: In a liquid crystal device, a first pixel area is provided in a pixel area of a first substrate, and a second pixel area is provided between the first pixel area and a seal material. The first pixel area has a first pixel electrode to which an image signal is applied, the image signal having a potential alternately switching between a positive polarity and a negative polarity with reference to a first central potential. The second pixel area includes a second pixel electrode to which a first driving potential is applied, the first driving potential having a potential alternately switching between a positive polarity and a negative polarity with reference to a second central potential, the first central potential and the second central potential having a potential difference set therebetween. Therefore, ionic impurities can be efficiently swept from the first pixel area to the second pixel area.

Abstract: In a liquid crystal device, a first pixel area is provided in a pixel area of a first substrate, and a second pixel area is provided between the first pixel area and a seal material. The first pixel area has a first pixel electrode to which an image signal is applied, the image signal having a potential alternately switching between a positive polarity and a negative polarity with reference to a first central potential. The second pixel area includes a second pixel electrode to which a first driving potential is applied, the first driving potential having a potential alternately switching between a positive polarity and a negative polarity with reference to a second central potential, the first central potential and the second central potential having a potential difference set therebetween. Therefore, ionic impurities can be efficiently swept from the first pixel area to the second pixel area.

Abstract: A chip serving as an individual substrate includes an internal circuit, and an external coupling terminal serving as a first coupling terminal arranged on a first side of the chip. One end side of the external coupling terminal is electrically coupled, via a first electrostatic protection circuit, to a guard line serving as a first common wiring extending along the first side, and another end side is electrically coupled to the internal circuit via a coupling wiring serving as a first coupling wiring. An internal circuit side of the coupling wiring is electrically coupled, via a second electrostatic protection circuit, to a guard line serving as a second common wiring extending along a second side intersecting the first side.

Abstract: In a transmissive-type electro-optical device, a plurality of pixel electrodes each overlap with each of a plurality of openings surrounded by a plurality of first light-shielding portions extending in a first direction and a plurality of second light-shielding portions extending in a second direction. A width of the first light-shielding portion is greater than a width of the second light-shielding portion. In the opening, a size thereof in the second direction is smaller than a size thereof in the first direction. A center of each of the pixel electrodes is shifted toward the pre-tilt orientation along the second direction from a center of each of the openings.

Abstract: A chip serving as an individual substrate includes an internal circuit, and an external coupling terminal serving as a first coupling terminal arranged on a first side of the chip. One end side of the external coupling terminal is electrically coupled, via a first electrostatic protection circuit, to a guard line serving as a first common wiring extending along the first side, and another end side is electrically coupled to the internal circuit via a coupling wiring serving as a first coupling wiring. An internal circuit side of the coupling wiring is electrically coupled, via a second electrostatic protection circuit, to a guard line serving as a second common wiring extending along a second side intersecting the first side.

Abstract: In a transmissive-type electro-optical device, a plurality of pixel electrodes each overlap with each of a plurality of openings surrounded by a plurality of first light-shielding portions extending in a first direction and a plurality of second light-shielding portions extending in a second direction. A width of the first light-shielding portion is greater than a width of the second light-shielding portion. In the opening, a size thereof in the second direction is smaller than a size thereof in the first direction. A center of each of the pixel electrodes is shifted toward the pre-tilt orientation along the second direction from a center of each of the openings.

Abstract: This core for a high-frequency acceleration cavity has shape formed with the single roll process by winding, with an interposed insulating layer, a Fe-based nanocrystal alloy thin strip having a roll contact surface and a free surface. The core for a high-frequency acceleration cavity is characterized in that projections having a crater-form depression are dispersed on the free surface of the Fe-based nanocrystal alloy thin strip, and the apexes of the projections are ground and blunted.

Abstract: An electrooptical apparatus includes an element substrate of which a first terminal group and a second terminal group for connecting each flexible substrate are sequentially formed thereon from a displaying portion. A signal wiring for supplying a video signal to a display control circuit for driving the displaying portion is dispersed and connected to the first terminal group and the second terminal group. In addition, a resistance of the signal wiring for the video signal which passes through the first terminal group and reaches the display control circuit and a resistance of the signal wiring for the video signal which passes through the second terminal group and reaches the display control circuit are substantially equal to each other.

Abstract: An electrooptical apparatus includes an element substrate of which a first terminal group and a second terminal group for connecting each flexible substrate are sequentially formed thereon from a displaying portion. A signal wiring for supplying a video signal to a display control circuit for driving the displaying portion is dispersed and connected to the first terminal group and the second terminal group. In addition, a resistance of the signal wiring for the video signal which passes through the first terminal group and reaches the display control circuit and a resistance of the signal wiring for the video signal which passes through the second terminal group and reaches the display control circuit are substantially equal to each other.

Abstract: An element substrate of electrooptical apparatus includes a first terminal group and a second terminal group for sequentially connecting a flexible substrate which are sequentially formed thereon from a display control circuit for driving a displaying portion, of which a signal wiring for a timing signal is connected to only the first terminal group, and a power source wiring with respect to the display control circuit is connected both of the first terminal group and the second terminal group. A signal wiring for supplying a select signal allocating the data line of the video signal is connected to only the first terminal group. Further, a signal wiring for supplying an enable signal which is a basis of a scanning pulse is dispersed and connected to the first terminal group and the second terminal group.

Abstract: A first static electricity protection circuit is provided with a first n-type transistor and a first p-type transistor, a second static electricity protection circuit is provided with at least one of a second n-type transistor and a second p-type transistor, a source is connected with a gate in these transistors, a gate of the first n-type transistor is electrically connected with a low potential power wiring VSS, a drain of the first n-type transistor is electrically connected with a signal wiring SL, a gate of the first p-type transistor is electrically connected with a high potential power wiring VDD, a drain of the first p-type transistor is electrically connected with the signal wiring SL, and a drain of at least one of the second n-type transistor and the second p-type transistor is electrically connected with the low potential power wiring VSS or the high potential power wiring VDD.

Abstract: In a static electricity protection circuit according to the invention, a first wiring is electrically connected to a drain of a first p-type transistor and a gate and a source of a first n-type transistor; a second wiring is electrically connected to a gate and a source of the first p-type transistor, a drain of the first n-type transistor, a drain of a second p-type transistor and a gate and a source of a second n-type transistor; and a third wiring is electrically connected to a gate and a source of the second p-type transistor and a drain of the second n-type transistor.

Abstract: In a static electricity protection circuit according to the invention, a first wiring is electrically connected to a drain of a first p-type transistor and a gate and a source of a first n-type transistor; a second wiring is electrically connected to a gate and a source of the first p-type transistor, a drain of the first n-type transistor, a drain of a second p-type transistor and a gate and a source of a second n-type transistor; and a third wiring is electrically connected to a gate and a source of the second p-type transistor and a drain of the second n-type transistor.

Abstract: This core for a high-frequency acceleration cavity has shape formed with the single roll process by winding, with an interposed insulating layer, a Fe-based nanocrystal alloy thin strip having a roll contact surface and a free surface. The core for a high-frequency acceleration cavity is characterized in that projections having a crater-form depression are dispersed on the free surface of the Fe-based nanocrystal alloy thin strip, and the apexes of the projections are ground and blunted.

Abstract: In a static electricity protection circuit according to the invention, a first wiring is electrically connected to a drain of a first p-type transistor and a gate and a source of a first n-type transistor; a second wiring is electrically connected to a gate and a source of the first p-type transistor, a drain of the first n-type transistor, a drain of a second p-type transistor and a gate and a source of a second n-type transistor; and a third wiring is electrically connected to a gate and a source of the second p-type transistor and a drain of the second n-type transistor.

Abstract: A first static electricity protection circuit is provided with a first n-type transistor and a first p-type transistor, a second static electricity protection circuit is provided with at least one of a second n-type transistor and a second p-type transistor, a source is connected with a gate in these transistors, a gate of the first n-type transistor is electrically connected with a low potential power wiring VSS, a drain of the first n-type transistor is electrically connected with a signal wiring SL, a gate of the first p-type transistor is electrically connected with a high potential power wiring VDD, a drain of the first p-type transistor is electrically connected with the signal wiring SL, and a drain of at least one of the second n-type transistor and the second p-type transistor is electrically connected with the low potential power wiring VSS or the high potential power wiring VDD.