Patents by Inventor Masaichi Shinoda

Masaichi Shinoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4349395
    Abstract: A metal layer of a metal-insulator-semiconductor type semiconductor device, e.g., a metal electrode on an oxide layer covering a semiconductor substrate of an MOS diode or an MOS FET, contains at least one cation-trapping element. The semiconductor substrate with the metal layer and the oxide layer is heated at an elevated temperature to diffuse some of the ions responsible for the cation-trapping element out of the metal layer and into the upper part of the oxide layer. The metal and oxide layers promote the surface passivation of the semiconductor device.
    Type: Grant
    Filed: December 18, 1980
    Date of Patent: September 14, 1982
    Assignee: Fujitsu Limited
    Inventors: Nobuo Toyokura, Hiroshi Tokunaga, Shinichi Inoue, Hajime Ishikawa, Masaichi Shinoda
  • Patent number: 4343657
    Abstract: In the production of a semiconductor device including an MISFET or a one transistor-one capacitor-memory cell, the excellent oxidation resistance of a silicon nitride film formed by direct nitridation, as well as the great oxidation tendency of a covering layer made of, for example, polycrystalline silicon selectively formed on the silicon nitride film, are utilized so as to form various regions of the semiconductor device in self alignment and to prevent a short circuit between such regions.A process according to the present invention comprises the steps of: selectively covering a semiconductor substrate with a relatively thick field insulation film; forming, on the exposed part of the semiconductor substrate, a relatively thin nitride film by direct nitridation; and selectively forming a film of silicon or a metal silicide on the silicon nitride film. A capacitor made of the silicon nitride is formed between the silicon or silicide film and the semiconductor substrate.
    Type: Grant
    Filed: July 31, 1980
    Date of Patent: August 10, 1982
    Assignee: Fujitsu Limited
    Inventors: Takashi Ito, Hajime Ishikawa, Masaichi Shinoda
  • Patent number: 4298629
    Abstract: In a method for forming an insulating film on a semiconductor substrate surface, the silicon nitride of the insulating film has been formed by a plasma CVD or a direct nitridation. In the present invention, a gas plasma of a nitrogen-containing gas is generated in a direct nitridation reaction chamber, and the semiconductor silicon body is heated to a temperature of from approximately 800 to approximately 1300.degree. C. within the gas plasma atmosphere, thereby forming the silicon nitride film. The resulting silicon nitride film has a dense structure and a low oxygen concentration and a thick silicon nitride film is formed in a short period by direct nitridation of silicon.
    Type: Grant
    Filed: March 7, 1980
    Date of Patent: November 3, 1981
    Assignee: Fujitsu Limited
    Inventors: Takao Nozaki, Takashi Ito, Hideki Arakawa, Hajime Ishikawa, Masaichi Shinoda
  • Patent number: 4270136
    Abstract: A metal layer of a metal-insulator-semiconductor type semiconductor device, e.g., a metal electrode on an oxide layer covering a semiconductor substrate of an MOS diode or an MOS FET, contains at least one cation-trapping element. The semiconductor substrate with the metal layer and the oxide layer is heated at an elevated temperature to diffuse some of the ions responsible for the cation-trapping element out of the metal layer and into the upper part of the oxide layer. The metal and oxide layers promote the surface passivation of the semiconductor device.
    Type: Grant
    Filed: March 23, 1979
    Date of Patent: May 26, 1981
    Assignee: Fujitsu Limited
    Inventors: Nobuo Toyokura, Hiroshi Tokunaga, Shinichi Inoue, Hajime Ishikawa, Masaichi Shinoda
  • Patent number: 4153906
    Abstract: This disclosure relates to an integrated circuit using an insulated gate field effect transistor of the punch-through type for use in high speed electronic computation. Until now the punch-through phenomena has been considered a defect in the insulated gate field effect transistor. However, the effective utilization of the punch-through phenomena is achieved by using a specially designed insulated gate field effect transistor having a selected structure or material.
    Type: Grant
    Filed: November 22, 1977
    Date of Patent: May 8, 1979
    Assignee: Fujitsu Limited
    Inventors: Masaichi Shinoda, Tetsuo Nakamura, Minoru Yamamoto