Patents by Inventor Masakatsu Takashita
Masakatsu Takashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8907420Abstract: A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.Type: GrantFiled: May 27, 2010Date of Patent: December 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Patent number: 8283720Abstract: A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers.Type: GrantFiled: March 18, 2008Date of Patent: October 9, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yauto Sumi, Masaru Izumisawa, Wataru Sekine, Hiroshi Ohta, Shoichiro Kurushima
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Patent number: 8227854Abstract: A semiconductor device includes: a drift layer having a superjunction structure; a semiconductor base layer selectively formed in a part of one surface of the drift layer; a first RESURF layer formed around a region having the semiconductor base layer formed thereon; a second semiconductor RESURF layer of a conductivity type which is opposite to a conductivity type of the first semiconductor RESURF layer; a first main electrode connected to a first surface of the drift layer; and a second main electrode connected to a second surface of the drift layer. The first RESURF layer is connected to the semiconductor base layer. The second semiconductor RESURF layer is in contact with the first semiconductor RESURF layer.Type: GrantFiled: November 7, 2007Date of Patent: July 24, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Wataru Saito, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Patent number: 8013360Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region.Type: GrantFiled: April 21, 2010Date of Patent: September 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta, Wataru Sekine
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Publication number: 20100230750Abstract: A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.Type: ApplicationFiled: May 27, 2010Publication date: September 16, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Publication number: 20100200936Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region.Type: ApplicationFiled: April 21, 2010Publication date: August 12, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta, Wataru Sekine
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Patent number: 7759732Abstract: A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.Type: GrantFiled: March 1, 2007Date of Patent: July 20, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Patent number: 7737469Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region.Type: GrantFiled: May 15, 2007Date of Patent: June 15, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta, Wataru Sekine
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Publication number: 20090302376Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type having a first surface and a second surface opposite to the first surface, a cell region, and a terminal region surrounding the cell region, the cell region being configured to allow a current to flow between the first surface and the second surface; a first guard ring layer of a second conductivity type selectively formed in a surface portion of the first semiconductor layer in the terminal region, the first guard ring layer having a bottom surface thereof and internal and external side surfaces thereof; and a second guard ring layer of the second conductivity type selectively formed in the surface portion of the first semiconductor layer in the terminal region so as to cover a portion of the first guard ring layer at which the bottom surface and the external side surface intersect.Type: ApplicationFiled: May 28, 2009Publication date: December 10, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoyuki INOUE, Wataru SAITO, Satoshi AIDA, Masakatsu TAKASHITA, Koichi ARATANI
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Patent number: 7622771Abstract: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.Type: GrantFiled: May 19, 2008Date of Patent: November 24, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Wataru Saito, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta, Wataru Sekine
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Publication number: 20090273031Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a major surface of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the major surface of the first semiconductor layer, the third semiconductor layer forming a structure of periodical arrangement with the second semiconductor layer; a fourth semiconductor layer of the second conductivity type provided above the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively provided on a surface of the fourth semiconductor layer; a first main electrode electrically connected to the first semiconductor layer; a second main electrode provided to contact a surface of the fifth semiconductor layer and a surface of the fourth semiconductor layer; and a control electrode provided above the fifth semiconductor layer, the fourth semiconductor layer, and the second semicondType: ApplicationFiled: March 20, 2009Publication date: November 5, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Syotaro ONO, Nana HATANO, Masakatsu TAKASHITA, Hiroshi OHTA, Miho WATANABE
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Patent number: 7605426Abstract: A power semiconductor device includes: a semiconductor substrate; a gate insulating film; a control electrode insulated from the semiconductor substrate by the gate insulating film; a first main electrode provided on a lower surface side of the semiconductor substrate; and a second main electrode provided on an upper surface side of the semiconductor substrate.Type: GrantFiled: November 1, 2007Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Publication number: 20080315297Abstract: There is provided a semiconductor device having a drift layer with a pillar structure including first semiconductor layer portions of the first conduction type and second semiconductor layer portions of the second conduction type formed in pillars alternately and periodically on a semiconductor substrate. A device region includes a plurality of arrayed transistors composed of the first semiconductor layer portions and the second semiconductor layer portions. A terminal region is formed at the periphery of the device region without the transistors formed therein. The drift layer in the terminal region has a carrier lifetime lower than ? the carrier lifetime in the drift layer in the device region.Type: ApplicationFiled: June 24, 2008Publication date: December 25, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masakatsu TAKASHITA, Yasuto SUMI, Masaru IZUMISAWA, Hiroshi OHTA, Wataru SAITO, Syotaro ONO
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Publication number: 20080290403Abstract: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.Type: ApplicationFiled: May 19, 2008Publication date: November 27, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Syotaro ONO, Wataru Saito, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta, Wataru Sekine
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Publication number: 20080246079Abstract: A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers.Type: ApplicationFiled: March 18, 2008Publication date: October 9, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yauto Sumi, Masaru Izumisawa, Wataru Sekine, Hiroshi Ohta, Shoichiro Kurushima
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Publication number: 20080135929Abstract: A power semiconductor device includes: a semiconductor substrate; a gate insulating film; a control electrode insulated from the semiconductor substrate by the gate insulating film; a first main electrode provided on a lower surface side of the semiconductor substrate; and a second main electrode provided on an upper surface side of the semiconductor substrate.Type: ApplicationFiled: November 1, 2007Publication date: June 12, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Publication number: 20080135926Abstract: A semiconductor device includes: a drift layer having a superjunction structure; a semiconductor base layer selectively formed in a part of one surface of the drift layer; a first RESURF layer formed around a region having the semiconductor base layer formed thereon; a second semiconductor RESURF layer of a conductivity type which is opposite to a conductivity type of the first semiconductor RESURF layer; a first main electrode connected to a first surface of the drift layer; and a second main electrode connected to a second surface of the drift layer. The first RESURF layer is connected to the semiconductor base layer. The second semiconductor RESURF layer is in contact with the first semiconductor RESURF layer.Type: ApplicationFiled: November 7, 2007Publication date: June 12, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Syotaro Ono, Wataru Saito, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Publication number: 20070272979Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region.Type: ApplicationFiled: May 15, 2007Publication date: November 29, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta, Wataru Sekine
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Publication number: 20070272977Abstract: A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.Type: ApplicationFiled: March 1, 2007Publication date: November 29, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Publication number: 20070267664Abstract: A semiconductor device according to the present invention comprises a first semiconductor layer of the first conductivity type. A pillar layer includes first semiconductor pillars of the first conductivity type and second semiconductor pillars of the second conductivity type arranged periodically and alternately on the first semiconductor layer. The first and second semiconductor pillar layer have a cross section in the shape of stripes in a planar direction. There is a semiconductor base layer of the second conductivity type selectively formed in a surface of the second semiconductor pillar, and a semiconductor diffusion layer of the first conductivity type selectively formed in a surface of the semiconductor base layer. The longitudinal direction of the shape of stripes is made almost same as the direction of pattern shift caused in the first semiconductor layer.Type: ApplicationFiled: May 21, 2007Publication date: November 22, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuto SUMI, Masakatsu Takashita, Masaru Izumisawa, Hiroshi Ohta, Wataru Saito, Syotaro Ono