Abstract: An operation path generation unit (210) generates an operation quantity time series for an actuator (111) based on a measurement state quantity output from a state sensor (101). A predictive model unit (220) generates a state quantity predictive time series by calculating a predictive model by using as an input the measurement state quantity and the operation quantity time series. A neural network unit (230) corrects the state quantity predictive time series by performing arithmetic operation of a neural network, by using as an input a measurement environment quantity output from an environment sensor (102) and the state quantity predictive time series. A state quantity evaluation unit (240) generates an evaluation result for the state quantity time series after the correction. The operation path generation unit outputs an operation quantity at the head of the operation quantity time series to the actuator when the evaluation result fulfils an appropriate criterion.

Abstract: In a simulation device (100), a calculation section (113) calculates an execution processing time required for executing each instruction code (221) of a plurality of instruction codes. A storage section (140) stores change setting information (230) in which a change rule that changes execution processing times of the plurality of instruction codes included in the processing unit is set. A change section (115) changes the execution processing time into a changed processing time according to the change rule being set in the change setting information (230). The change section (115) also includes the changed processing time of each instruction code of the plurality of instruction codes, in an entire time point (240). A simulation execution section (116) executes a simulation of a target program (210) using the entire time point (240). A monitoring section (120) monitors a status of a target model during execution of the simulation.

Abstract: In a simulation device (100), a calculation section (113) calculates an execution processing time required for executing each instruction code (221) of a plurality of instruction codes. A storage section (140) stores change setting information (230) in which a change rule that changes execution processing times of the plurality of instruction codes included in the processing unit is set. A change section (115) changes the execution processing time into a changed processing time according to the change rule being set in the change setting information (230). The change section (115) also includes the changed processing time of each instruction code of the plurality of instruction codes, in an entire time point (240). A simulation execution section (116) executes a simulation of a target program (210) using the entire time point (240). A monitoring section (120) monitors a status of a target model during execution of the simulation.

Abstract: A simulation device executes simulation of a program including a first function and a second function that are similar to each other. An address information storage unit stores address information in which a first start address and a first end address of the first function are associated with a second start address and a second end address of the second function. When an original address is in between the first start address and the first end address, an address rearrangement unit rearranges the original address to between the second start address and the second end address as a processing address. An evaluation unit executes cache simulation on the processing address, to evaluate whether to be a cache hit or a cache miss.

Abstract: An application process is switched between asymmetric processor cores having no compatibility in instruction set architectures so that the process can be continuously executed. In an information processing device, when a request to switch an execution subject is generated while a first processor core is executing an application program, a switch process code makes the first processor core specify a basic block being executed at present. The switch process code makes the first processor core execute a first execution code until a branch instruction at the end of the specified basic block, and makes a second processor core execute a second execution code from an instruction at the head of a basic block to be executed next to the specified basic block.

Abstract: An application process is switched between asymmetric processor cores having no compatibility in instruction set architectures so that the process can be continuously executed. In an information processing device, when a request to switch an execution subject is generated while a first processor core is executing an application program, a switch process code makes the first processor core specify a basic block being executed at present. The switch process code makes the first processor core execute a first execution code until a branch instruction at the end of the specified basic block, and makes a second processor core execute a second execution code from an instruction at the head of a basic block to be executed next to the specified basic block.