Abstract: A semiconductor device is manufactured by forming, on an insulating base material, a first support element having a side face that extends from a surface of the insulating base material, forming a coating of amorphous silicon on the side face of the first support element, filling an aperture disposed between the first support element and a second support element that extends from a surface of the insulating base material with an insulating film, planarizing the insulating film to expose an exposed portion of the coating and a surface of the first support element, and siliciding the amorphous silicon of the coating to form an interconnect.

Abstract: A semiconductor device is manufactured by forming, on an insulating base material, a first support element having a side face that extends from a surface of the insulating base material, forming a coating of amorphous silicon on the side face of the first support element, filling an aperture disposed between the first support element and a second support element that extends from a surface of the insulating base material with an insulating film, planarizing the insulating film to expose an exposed portion of the coating and a surface of the first support element, and siliciding the amorphous silicon of the coating to form an interconnect.

Abstract: A semiconductor device includes: a first source region and a first drain region formed at a distance from each other in a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate between the first source region and the first drain region; a first gate electrode formed on the first gate insulating film; a first source electrode formed above the first source region and including a ferromagnetic layer having an easy axis of magnetization in a first direction; a first drain electrode formed above the first drain region and including a ferromagnetic layer magnetized in a second direction at an angle larger than 0 degrees but not larger than 180 degrees with respect to the first direction; and a second drain electrode formed above the first drain region, being located at a distance from the first drain electrode, and including a ferromagnetic layer magnetized in a direction substantially antiparallel to the second direction.

Abstract: Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-containing NiSi layer formed on the diffusion regions and containing F atoms at a concentration of 3.0×1013 cm?2 or more in areal density, wherein a depth from the junction position formed between the diffusion region and the semiconductor substrate to the bottom of the F-containing NiSi layer is confined within the range of 20 to 100 nm, and the concentration of F atoms at an interface between the F-containing NiSi layer and the semiconductor substrate is 8.0×1018 cm?3 or more.

Abstract: A semiconductor device includes: a first MOSFET including: first source and drain regions formed at a distance from each other in a first semiconductor region; a first insulating film formed on the first semiconductor region between the first source region and the first drain region; a first gate electrode formed on the first insulating film; a first sidewall insulating film formed at side portions of the first gate electrode; a first single-crystal silicon layer formed on each of the first source and drain regions, and having at least an upper-face made of a {111} plane; a first NiSi layer formed at least on the first single-crystal silicon layer, and having a portion whose interface with the first single-crystal silicon is on the {111} plane of the first single-crystal silicon layer and a part of the portion of the first NiSi layer being in contact with the first sidewall insulating film; and a first TiN film being in contact with the portion of the first NiSi layer on the {111} plane of the first single-cr

Abstract: A semiconductor device includes a semiconductor substrate, a monocrystalline channel region of a first conductivity type formed on the surface of the semiconductor substrate, a gate electrode formed on the channel region via a gate insulating film, a pair of source/drain electrodes of a second conductivity type provided on both sides of the gate electrode, metallic compound layers formed on the source/drain electrodes, stress application layers located under the respective source and drain electrodes and each having a crystal structure whose intrinsic lattice spacing is different from lattice spacing inherent in a substance constituting the source/drain electrodes, and first buried insulating regions disposed under the respective stress application layers.

Abstract: A method of fabricating a semiconductor device having a pair of shallow silicided source and drain junctions with minimal leakage is disclosed. The semiconductor device typically has a MISFET structure with NiSi regions partially making up the source and drain regions. The fabrication method includes the steps of providing silicon surfaces having Si{110} crystal planes on both sides of this gate electrode and forming a plurality of nickel silicide (NiSi) regions, each having a rectangular planar shape whose shorter sides being equal or less than 0.5 ?m in length and running along a Si<100> direction.

Abstract: A MOS semiconductor device includes a substrate having a first region with a Si(110) surface and a second region with a Si(100) surface, a p-channel MOSFET formed in the first region, and an n-channel MOSFET formed in the second region. The p-channel MOSFET including a first silicide layer formed on source/drain regions, and containing N atoms at an areal density of 8.5×1013 to 8.5×1014 cm?2, and F atoms at an areal density of less than 5.0×1012 cm?2. The n-channel MOSFET including a second silicide layer formed on a source/drain regions, and containing F atoms at an areal density of not less than 5.0×1013 cm?2.

Abstract: A semiconductor device of complementary structure with increased carrier mobilities of both polarities by applying orientation-dependent mechanical stresses to their respective semiconductor channel regions, comprises a semiconductor region subjected to compressive stress in a first direction along a surface and tensile stress in a second direction different from the first direction, a field effect transistor of a first conductivity type formed in the semiconductor region and including source and drain regions separately arranged along the first direction and a field effect transistor of a second conductivity type formed in the semiconductor region and including source and drain regions separately arranged along the second direction.

Abstract: A MOSFET-type semiconductor device includes a monocrystalline semiconductor layer formed in a shape of a thin wall on a insulating film, a gate electrode straddling over the semiconductor layer around the middle portion of the wall-shaped semiconductor layer via a gate insulating film, source and drain regions formed at the both ends of the semiconductor layer, a first metal-semiconductor compound layer formed on one of the side walls of each of source and drain regions of the semiconductor layer, and a second metal-semiconductor compound layer having a different composition and Schottky barrier height from that of the first metal-semiconductor compound layer on the other side wall of each of source and drain regions of the semiconductor layer.

Abstract: Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-containing NiSi layer formed on the diffusion regions and containing F atoms at a concentration of 3.0×1013 cm?2 or more in areal density, wherein a depth from the junction position formed between the diffusion region and the semiconductor substrate to the bottom of the F-containing NiSi layer is confined within the range of 20 to 100 nm, and the concentration of F atoms at an interface between the F-containing NiSi layer and the semiconductor substrate is 8.0×1018 cm?3 or more.

Abstract: Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-containing NiSi layer formed on the diffusion regions and containing F atoms at a concentration of 3.0×1013 cm?2 or more in areal density, wherein a depth from the junction position formed between the diffusion region and the semiconductor substrate to the bottom of the F-containing NiSi layer is confined within the range of 20 to 100 nm, and the concentration of F atoms at an interface between the F-containing NiSi layer and the semiconductor substrate is 8.0×1018 cm?3 or more.

Abstract: A semiconductor device includes: a first source region and a first drain region formed at a distance from each other in a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate between the first source region and the first drain region; a first gate electrode formed on the first gate insulating film; a first source electrode formed above the first source region and including a ferromagnetic layer having an easy axis of magnetization in a first direction; a first drain electrode formed above the first drain region and including a ferromagnetic layer magnetized in a second direction at an angle larger than 0 degrees but not larger than 180 degrees with respect to the first direction; and a second drain electrode formed above the first drain region, being located at a distance from the first drain electrode, and including a ferromagnetic layer magnetized in a direction substantially antiparallel to the second direction.

Abstract: A semiconductor device includes: a first MOSFET including: first source and drain regions formed at a distance from each other in a first semiconductor region; a first insulating film formed on the first semiconductor region between the first source region and the first drain region; a first gate electrode formed on the first insulating film; a first sidewall insulating film formed at side portions of the first gate electrode; a first single-crystal silicon layer formed on each of the first source and drain regions, and having at least an upper-face made of a {111} plane; a first NiSi layer formed at least on the first single-crystal silicon layer, and having a portion whose interface with the first single-crystal silicon is on the {111} plane of the first single-crystal silicon layer and a part of the portion of the first NiSi layer being in contact with the first sidewall insulating film; and a first TiN film being in contact with the portion of the first NiSi layer on the {111} plane of the first single-cr

Abstract: A MOSFET-type semiconductor device includes a monocrystalline semiconductor layer formed in a shape of a thin wall on a insulating film, a gate electrode straddling over the semiconductor layer around the middle portion of the wall-shaped semiconductor layer via a gate insulating film, source and drain regions formed at the both ends of the semiconductor layer, a first metal-semiconductor compound layer formed on one of the side walls of each of source and drain regions of the semiconductor layer, and a second metal-semiconductor compound layer having a different composition and Shottky barrier height from that of the first metal-semiconductor compound layer on the other side wall of each of source and drain regions of the semiconductor layer.

Abstract: A MOSFET-type semiconductor device includes a monocrystalline semiconductor layer formed in a shape of a thin wall on a insulating film, a gate electrode straddling over the semiconductor layer around the middle portion of the wall-shaped semiconductor layer via a gate insulating film, source and drain regions formed at the both ends of the semiconductor layer, a first metal-semiconductor compound layer formed on one of the side walls of each of source and drain regions of the semiconductor layer, and a second metal-semiconductor compound layer having a different composition and Shottky barrier height from that of the first metal-semiconductor compound layer on the other side wall of each of source and drain regions of the semiconductor layer.

Abstract: A method of fabricating a semiconductor device having a pair of shallow silicided source and drain junctions with minimal leakage is disclosed. The semiconductor device typically has a MISFET structure with NiSi regions partially making up the source and drain regions. The fabrication method includes the steps of providing silicon surfaces having Si{110} crystal planes on both sides of this gate electrode and forming a plurality of nickel silicide (NiSi) regions, each having a rectangular planar shape whose shorter sides being equal or less than 0.5 ?m in length and running along a Si<100> direction.

Abstract: A method for manufacturing a MOSFET equipped with a silicide layer over shallow source and drain junctions without leakage generation is provided. By restricting the temperature of manufacturing steps after the silicide formation below a critical temperature Tc, which is defined below as a function of a junction depth Dj from 20 nm to 60 nm, leakage generation is practically suppressed. Tc = a × Dj + b , ? where a = 6.11 ? ( 20 < Dj ? 26 ) = 1.60 ? ( 26 < Dj ? 60 ) , ? b = 290.74 ? ( 20 < Dj ? 26 ) = 408 ? ( 26 < Dj ? 60 ) , Dj is a junction depth (nm) measured from the lower surface of the silicide layer, and Tc is a critical temperature (° C.) during a heat treatment.

Abstract: A MOS semiconductor device includes a substrate having a first region with a Si(110) surface and a second region with a Si(100) surface, a p-channel MOSFET formed in the first region, and an n-channel MOSFET formed in the second region. The p-channel MOSFET including a first silicide layer formed on source/drain regions, and containing N atoms at an areal density of 8.5×1013 to 8.5×1014 cm?2, and F atoms at an areal density of less than 5.0×1012 cm?2. The n-channel MOSFET including a second silicide layer formed on a source/drain regions, and containing F atoms at an areal density of not less than 5.0×1013 cm?2.

Abstract: A semiconductor device of complementary structure with increased carrier mobilities of both polarities by applying orientation-dependent mechanical stresses to their respective semiconductor channel regions, comprises a semiconductor region subjected to compressive stress in a first direction along a surface and tensile stress in a second direction different from the first direction, a field effect transistor of a first conductivity type formed in the semiconductor region and including source and drain regions separately arranged along the first direction and a field effect transistor of a second conductivity type formed in the semiconductor region and including source and drain regions separately arranged along the second direction.