Abstract: A display comprises a relatively large plurality of picture elements in each of the vertical and horizontal directions, with which characters are displayed with a relatively less plurality of picture elements in each of the vertical and horizontal directions. In order to store the data to be displayed with the above described display, a refresh memory is employed. The refresh memory is used such that the respective areas thereof storing portions of the character are addressed in synchronism with the period of a character clock, whereby the character data to be displayed is read out therefrom. Each portion of the character data as read out from the refresh memory is latched in a latch circuit during the character clock period and is kept supplied to the display. The refresh memory serves to renew portions of the character at an arbitrary timing during the display period by the display or during the blanking period where display is not made by the display.

Abstract: A direct memory access control apparatus performs direct data transfer between a memory and an input/output controller in a data processing system. When the system is placed in a direct memory access mode upon receipt of a direct memory access request from the input/output controller, a data bus connected between the input/output controller and the memory is separated from a central processing unit by means of a data bus separating circuit, and an address bus of the memory is also separated from the central processing unit by means of an address bus switch circuit. The address bus of the memory is connected to a direct memory access controller by means of the address bus switch circuit. Therefore, the memory is addressed by the direct memory access controller through the address bus while the data is directly transferred between the memory and the input/output device through the data bus.