Patents by Inventor Masakazu Hamada
Masakazu Hamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250041794Abstract: A humidity-controlling material includes: a water-absorbing body containing a water-absorbing material; and a humidity-controlling component configured to be present in the water-absorbing material and to absorb or release moisture, wherein the humidity-controlling component includes: a first salt containing first anions and first cations and having a deliquescence point in a relative humidity range of from 30% RH to 80% RH both inclusive; and a second salt containing second anions that differ from the first anions and second cations that differ from the first cations.Type: ApplicationFiled: November 29, 2022Publication date: February 6, 2025Inventors: Yuusuke SHIMIZU, TSUYOSHI KAMADA, MASAKAZU KAMURA, TETSUYA IDE, SHO OCHI, KYOKO MATSUURA, HIROKA HAMADA, SATORU MOTONAMI
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Patent number: 11837516Abstract: In a semiconductor device, on a heat dissipation portion of a lead frame opposite to a mounting portion on which a semiconductor element is mounted, a thin molding portion having a thickness of about 0.02 mm to 0.3 mm is formed by a second molding resin which is a high-heat-dissipation resin. A scale-like portion on which scale-shaped projections are consecutively formed is provided over both sides across a resin boundary portion of the heat dissipation portion. The scale-like portion reaches abutting surfaces of an upper die and a lower die of a mold used in a molding process. Thus, the same void inhibition effect as with an air vent is obtained.Type: GrantFiled: September 6, 2018Date of Patent: December 5, 2023Assignee: Mitsubishi Electric CorporationInventors: Takanobu Kajihara, Katsuhiko Omae, Takashi Nagao, Atsuki Fujita, Ryosuke Takeshita, Masakazu Hamada
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Publication number: 20210305111Abstract: In a semiconductor device, on a heat dissipation portion of a lead frame opposite to a mounting portion on which a semiconductor element is mounted, a thin molding portion having a thickness of about 0.02 mm to 0.3 mm is formed by a second molding resin which is a high-heat-dissipation resin. A scale-like portion on which scale-shaped projections are consecutively formed is provided over both sides across a resin boundary portion of the heat dissipation portion. The scale-like portion reaches abutting surfaces of an upper die and a lower die of a mold used in a molding process. Thus, the same void inhibition effect as with an air vent is obtained.Type: ApplicationFiled: September 6, 2018Publication date: September 30, 2021Applicant: Mitsubishi Electric CorporationInventors: Takanobu KAJIHARA, Katsuhiko OMAE, Takashi NAGAO, Atsuki FUJITA, Ryosuke TAKESHITA, Masakazu HAMADA
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Patent number: 9673139Abstract: A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate. The first wiring is formed on the first insulating film. The second insulating film is provided on the first insulating film to cover the first wiring. The second wiring is formed on the second insulating film. Furthermore, the second insulating film has a first opening part and a second opening part which expose the first wiring. The second wiring has a seed layer and a first plating layer. The first plating layer covers an entire side surface of the seed layer. The seed layer is not provided in the second opening part and a periphery thereof.Type: GrantFiled: May 20, 2016Date of Patent: June 6, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroshige Hirano, Michinari Tetani, Masakazu Hamada, Nobuaki Tarumi
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Publication number: 20170133500Abstract: A nitride semiconductor device according to the present disclosure includes a substrate, a p-type GaN layer formed on a main surface of the substrate and made of AlxInyGa1-x-yN containing p-type impurities, where 0?X<1, 0?Y<1, and a Ti film formed on the p-type GaN layer. The Ti film is in a coherent or metamorphic state with respect to the p-type GaN layer.Type: ApplicationFiled: January 25, 2017Publication date: May 11, 2017Inventors: Ryuuji ETOU, Takeshi HARADA, Masakazu HAMADA, Tamotsu SHIBATA
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Publication number: 20160268184Abstract: A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate. The first wiring is formed on the first insulating film. The second insulating film is provided on the first insulating film to cover the first wiring. The second wiring is formed on the second insulating film. Furthermore, the second insulating film has a first opening part and a second opening part which expose the first wiring. The second wiring has a seed layer and a first plating layer. The first plating layer covers an entire side surface of the seed layer. The seed layer is not provided in the second opening part and a periphery thereof.Type: ApplicationFiled: May 20, 2016Publication date: September 15, 2016Inventors: HIROSHIGE HIRANO, MICHINARI TETANI, MASAKAZU HAMADA, NOBUAKI TARUMI
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Patent number: 7564133Abstract: A semiconductor device comprises: a lower interconnect formed over a semiconductor substrate; an insulating film formed on the lower interconnect; a via hole penetrating the insulating film to reach the lower interconnect; a first barrier film covering bottom and side surfaces of the via hole; and a metal film filling the via hole covered with the first barrier film. A portion of the first barrier film covering a lower end of the side surface of the via hole is thicker than a portion covering the bottom surface of the via hole.Type: GrantFiled: April 4, 2006Date of Patent: July 21, 2009Assignees: Panasonic Corporation, Renesas Technology, Corp.Inventors: Masakazu Hamada, Kazuyoshi Maekawa, Kenichi Mori
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Publication number: 20070145600Abstract: A semiconductor device includes an embedded wire in a first wire trench formed in a first interlayer dielectric film, the embedded wire having a barrier metal, a first seed film, a second seed film, and a copper film. The first seed film is formed by a copper film containing metal, and the second film is formed by a copper film. The second seed film suppresses that the metal contained in the first seed film diffuses into a wiring material film in a manufacturing process.Type: ApplicationFiled: December 28, 2006Publication date: June 28, 2007Inventors: Hisashi Yano, Masakazu Hamada, Kazuyoshi Maekawa, Kenichi Mori
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Publication number: 20070145591Abstract: The semiconductor device manufacturing method includes the steps of: applying a first wire including a barrier metal film, a seed film, and a wiring material film in a first wire trench formed in a first interlayer dielectric film; after a second interlayer dielectric film is formed on the first interlayer dielectric film, forming a via hole and a second wire trench in the second interlayer dielectric film so as to expose the wiring material film; applying a barrier metal film on the semiconductor device; and after the barrier metal film on the wiring material film is removed by using, for example, a re-sputtering process, applying a barrier metal film on the wiring material film. The re-sputtering process can remove an oxide film of impurity metal in the seed film applied on the wiring material film.Type: ApplicationFiled: December 28, 2006Publication date: June 28, 2007Inventors: Hisashi Yano, Masakazu Hamada, Kazuyoshi Maekawa, Kenichi Mori
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Publication number: 20070085211Abstract: A second interlayer insulating film is formed on a first interlayer insulating film and a wiring including a Cu film, and a via and a trench are formed in the second interlayer insulating film so as to expose the Cu film. After a hollow having an inner diameter larger than that of the via is formed in the Cu film, a first barrier metal film is formed. Subsequently, the first barrier metal film is re-sputtered to fill the hollow with the first barrier metal film and to extend the via so as to have a rounded lower part. Next, a second barrier metal film and a Cu film are formed sequentially in the via and the trench. Then, the Cu film, the second barrier metal film, and the first barrier metal film on the second interlayer insulating film are removed.Type: ApplicationFiled: July 11, 2006Publication date: April 19, 2007Inventor: Masakazu Hamada
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Publication number: 20060223325Abstract: A semiconductor device comprises: a lower interconnect formed over a semiconductor substrate; an insulating film formed on the lower interconnect; a via hole penetrating the insulating film to reach the lower interconnect; a first barrier film covering bottom and side surfaces of the via hole; and a metal film filling the via hole covered with the first barrier film. A portion of the first barrier film covering a lower end of the side surface of the via hole is thicker than a portion covering the bottom surface of the via hole.Type: ApplicationFiled: April 4, 2006Publication date: October 5, 2006Inventors: Masakazu Hamada, Kazuyoshi Maekawa, Kenichi Mori
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Patent number: 6100112Abstract: A bump-attached tape carrier for mounting a semiconductor chip on a circuit substrate, the bump-attached tape carrier comprising, an insulating film, a conductor pattern formed on the insulating film, and metal bumps formed on the conductor pattern and adapted to be bonded with the semiconductor chip, wherein the metal bumps are respectively formed of a columnar body having a side wall substantially perpendicular to the conductor pattern.Type: GrantFiled: October 6, 1998Date of Patent: August 8, 2000Assignee: The Furukawa Electric Co., Ltd.Inventors: Toshiaki Amano, Toshiaki Asada, Masakazu Hamada
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Patent number: 5083401Abstract: A rotor is formed by rotationally cutting a metal mass mounted on a machine tool shaft under computer control, and also its outer periphery is formed with annular grooves by rotational cutting. The rotor is rotated on a shaft while feeding an abrasive to it, while a workpiece set on a stage movable along three perpendicular axes, i.e., X-, Y and Z-axes, urged against the rotor by moving the stage in the Z-axis direction. The surface of the workpiece is polished by causing the stage to be moved in the X-axis direction and reciprocated in the Y-axis direction, the urging pressure being controlled by measuring it with a pressure sensor.Type: GrantFiled: February 23, 1989Date of Patent: January 28, 1992Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Mikio Yamashita, Shigekazu Hara, Hiroyuki Matsunaga, Tooru Mamiya, Masakazu Hamada