Patents by Inventor Masakazu Hashizume

Masakazu Hashizume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7453147
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: November 18, 2008
    Assignees: Renesas Technology Corp., Renesas Eastern Semiconductor, Inc.
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi
  • Patent number: 7119004
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: October 10, 2006
    Assignees: Renesas Technology Corp., Renesas Eastern Japan semiconductor, Inc.
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi
  • Publication number: 20060118970
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Application
    Filed: January 6, 2006
    Publication date: June 8, 2006
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi
  • Publication number: 20040245655
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Application
    Filed: February 13, 2004
    Publication date: December 9, 2004
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi
  • Patent number: 6709890
    Abstract: In a method of manufacturing a high frequency module to be assembled by providing, on a wiring board, a chip part and a semiconductor pellet to be bare chip mounted and then mounting the chip part and the semiconductor pellet through soldering, the wiring board is separated from a heat block with the semiconductor pellet pressurized against the wiring board in a main heating portion heating and melting a reflow solder, thereby cooling a soldering portion. Consequently, the generation of a void in the soldering portion can be prevented and the connecting reliability of the soldering portion can be enhanced. In addition, a degree of mounting horizontality of the semiconductor pellet on the wiring board can be enhanced.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: March 23, 2004
    Assignees: Renesas Technology Corporation, Hitachi Tobu Semiconductor Ltd.
    Inventors: Tsutomu Ida, Akio Ishizu, Masakazu Hashizume, Isao Hagiwara, Yoshinori Shiokawa
  • Publication number: 20010014490
    Abstract: In a method of manufacturing a high frequency module to be assembled by providing, on a wiring board, a chip part and a semiconductor pellet to be bare chip mounted and then mounting the chip part and the semiconductor pellet through soldering, the wiring board is separated from a heat block with the semiconductor pellet pressurized against the wiring board in a main heating portion heating and melting a reflow solder, thereby cooling a soldering portion. Consequently, the generation of a void in the soldering portion can be prevented and the connecting reliability of the soldering portion can be enhanced. In addition, a degree of mounting horizontality of the semiconductor pellet on the wiring board can be enhanced.
    Type: Application
    Filed: February 15, 2001
    Publication date: August 16, 2001
    Inventors: Tsutomu Ida, Akio Ishizu, Masakazu Hashizume, Isao Hagiwara, Yoshinori Shiokawa