Patents by Inventor Masakazu Ishino
Masakazu Ishino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8937390Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: GrantFiled: March 6, 2014Date of Patent: January 20, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
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Publication number: 20140183730Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: ApplicationFiled: March 6, 2014Publication date: July 3, 2014Inventors: Nae HISANO, Shigeo OHASHI, Yasuo OSONE, Yasuhiro NAKA, Hiroyuki TENMEI, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO, Hideharu MIYAKE, Shiro UCHIYAMA
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Patent number: 8704352Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: GrantFiled: January 6, 2010Date of Patent: April 22, 2014Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
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Patent number: 8513121Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.Type: GrantFiled: September 15, 2012Date of Patent: August 20, 2013Assignee: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Kayoko Shibata
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Publication number: 20130011967Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.Type: ApplicationFiled: September 15, 2012Publication date: January 10, 2013Inventors: Masakazu Ishino, Hiroaki Ikeda, Kayoko Shibata
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Patent number: 8334465Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.Type: GrantFiled: September 30, 2008Date of Patent: December 18, 2012Assignee: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Hideharu Miyake, Shiro Uchiyama, Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano
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Patent number: 8298940Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.Type: GrantFiled: January 12, 2011Date of Patent: October 30, 2012Assignee: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Kayoko Shibata
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Publication number: 20110104852Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.Type: ApplicationFiled: January 12, 2011Publication date: May 5, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Masakazu ISHINO, Hiroaki Ikeda, Kayoko Shibata
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Patent number: 7893540Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.Type: GrantFiled: August 7, 2009Date of Patent: February 22, 2011Assignee: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Kayoko Shibata
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Patent number: 7791196Abstract: A semiconductor package includes a uniform thin insulating film covering the internal circuit formed on a silicon substrate. A plurality of thick island insulating films are formed underlying respective pad electrodes, which connect the internal circuit to an external circuit. The silicon substrate is polished from the bottom to have a thickness less than 0.6 mm. The thick island insulating films reduces an electrostatic capacitance of the pad electrodes to reduce the propagation delay of a signal passing through the pad electrodes.Type: GrantFiled: April 27, 2007Date of Patent: September 7, 2010Assignee: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda
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Patent number: 7754581Abstract: A method for manufacturing a semiconductor device includes the steps of forming first and second semiconductor wafers each including an array of chips and elongate electrodes, forming a groove on scribe lines separating the chips from one another; coating a surface of one of the semiconductor wafers with adhesive; bonding together the semiconductor wafers while allowing the groove to receive therein excessive adhesive; and heating the wafers to connect the elongate electrodes of both the semiconductor wafers.Type: GrantFiled: December 14, 2007Date of Patent: July 13, 2010Assignee: Elpida Memory, Inc.Inventors: Hiroaki Ikeda, Masakazu Ishino, Hiroyuki Tenmei, Naoya Kanda, Yasuhiro Naka, Kunihiko Nishi
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Publication number: 20100171213Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: ApplicationFiled: January 6, 2010Publication date: July 8, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Nae HISANO, Shigeo OHASHI, Yasuo OSONE, Yasuhiro NAKA, Hiroyuki TENMEI, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO, Hideharu MIYAKE, Shiro UCHIYAMA
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Patent number: 7638362Abstract: A memory module of the present invention has a memory core chip for storing information, an interface chip for controlling data input/output, an interposer chip for transmitting/receiving data to/from the outside, and an external connection terminal provided in closest proximity to the interposer chip. A heat dissipating plate is provided in closest proximity to the interface chip. The interposer chip has a substrate made of a semiconductor material that is similar to the memory core chip, a land for holding the external connection terminal, a wire connected to the external connection terminal, and an insulating film for insulating the wire. The land, wire, and insulating film are integrally formed on one surface of the interposer chip.Type: GrantFiled: May 9, 2006Date of Patent: December 29, 2009Assignee: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda
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Publication number: 20090294990Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.Type: ApplicationFiled: August 7, 2009Publication date: December 3, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Masakazu ISHINO, Hiroaki IKEDA, Kayoko SHIBATA
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Patent number: 7618847Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.Type: GrantFiled: August 7, 2008Date of Patent: November 17, 2009Assignees: Elpida Memory, Inc., Hitachi, Ltd.Inventors: Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano, Hiroaki Ikeda, Masakazu Ishino
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Patent number: 7576433Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.Type: GrantFiled: June 28, 2006Date of Patent: August 18, 2009Assignee: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Kayoko Shibata
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Patent number: 7564127Abstract: A memory module of the present invention is provided with a memory core chip that is placed between an interface chip and an interposer chip and has a relay wire for electrically connecting these chips, an interposer chip that transmits type-information, that is information showing the type of the memory core chip, to the interface chip through the relay wire, and the interface chip that controls the memory core chip in accordance with the type-information received from the interposer chip.Type: GrantFiled: April 17, 2006Date of Patent: July 21, 2009Assignee: Elpida Memory, Inc.Inventors: Hiroaki Ikeda, Masakazu Ishino
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Publication number: 20090134498Abstract: The present invention includes a semiconductor element provided with an electrode passing through front and back sides. The electrode is formed as a cylinder including a hollow portion, and stress relaxing material is provided in the hollow portion, which is used to reduce stress that is induced between the semiconductor element and the electrode. The stress relaxing material is an elastic body made of resin material.Type: ApplicationFiled: November 19, 2008Publication date: May 28, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Hiroaki IKEDA, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama, Yasuhiro Naka, Nae Hisano, Hisashi Tanie, Kunihiko Nishi, Hiroyuki Tenmei
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Publication number: 20090109641Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.Type: ApplicationFiled: September 30, 2008Publication date: April 30, 2009Applicant: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Hideharu Miyake, Shiro Uchiyama, Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano
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Publication number: 20090072414Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.Type: ApplicationFiled: August 7, 2008Publication date: March 19, 2009Inventors: Hiroyuki TENMEI, Kunihiko NISHI, Yasuhiro NAKA, Nae HISANO, Hiroaki IKEDA, Masakazu ISHINO