Abstract: Power consumption by a processor can be reduced without impairing the efficiency of processing by the processor. When a processor 2 inquires the operating status of a DMA controller 4 during a DMA operation, a clock controller 5 stops the supply of a clock signal to the processor 2 to prohibit the processor 2 from making inquiries about the operating status of the DMA controller 4. According to this arrangement, the processor 2 can continue processing until the processor 2 inquires the operating status of the DMA controller 4, that is, until it outputs a state-indication-register-read request signal, even if the DMA operation is being performed in the DMA controller 4. When the processor 2 outputs a state-indication-register-read request signal, the clock signal supply to the processor 2 is stopped.

Abstract: The object of the invention is to efficiently perform indirect index vector reference. An element register of a vector register or a scalar register specified in the “index” is divided into multiple areas, and a particular index vector is acquired by selecting any of the divided areas. Accordingly, it is possible to store substantially multiple index vectors in one vector register, and therefore register resources can be efficiently used. The procedure for providing index vectors is similar to that for providing one index vector, and therefore the code size and the process cycles of the program are almost not increased. That is, according to the present invention, indirect index vector reference can be more efficiently performed.

Abstract: The object of the invention is to efficiently perform a vector operation using a vector register. A vector processor is provided with a vector register forming a ring buffer, and any address of the ring buffer can be specified as the top address. Accordingly, when multiple vector data to be processed are overlapped, it is possible to circularly read or write the vector data stored in one vector register without storing the vector data in separate vector registers. Thus, it is possible to prevent the same data from being redundantly read as well as to decrease register resources to be required, thereby enabling an efficient vector operation using a vector register.

Abstract: To provide a method of using a memory that can contribute to an efficient SIMD operation. The method of using the memory includes the steps of: supposing a predefined two dimensional memory space consisting of predefined virtual minimum two dimensional memory spaces 1 arranged in longitudinal and transverse directions; and preassigning each address of the virtual minimum two dimensional memory space 1 to an address in each of n physical memories determined in relation with the virtual minimum two dimensional memory space.

Abstract: A data encoding method of a multiple-valued information source in accordance with the present invention includes a prediction setting process which divides a multiple-valued information source into bit planes or level planes, defines either "0" or "1" of the plane as a superior symbol and the other as an inferior symbol, and predicting the superior symbol to continue for n units, and sets the n units as a prediction bit number run, and a prediction result output process which outputs either signal of "0" or "1" as a prediction correct signal as a code word, when prediction is correct for an observed series that includes the prediction bit number input, and moves to the operation of encoding the next string of n bits, or outputs the other of either "0" or "1" as a prediction failed signal as a code word, when the prediction has failed in the encoding operation.

Abstract: A data encoding method having a prediction setting process that designates a numerically superior symbol as either a "0" or a "1", and the other one is designated as a numerically inferior symbol. Then a binary bit string composed of "0"s and "1"s is input, and the numerically superior symbol is predicted to continuously repeat for n symbols, where n is set as a prediction bit number. A prediction result output process outputs a prediction correct signal that is either a "0" or a "1" when a prediction is correct for the observed series. The process then moves to an operation to perform encoding of a bit series containing the next n symbols, or otherwise outputs the other signal (i.e., that is not used to represent that the prediction is correct) as a prediction failure signal.