Abstract: An n+ layer 3a connected to a source line SL at both ends, an n+ layer 3b connected to a bit line BL, a first gate insulating layer 4a formed on a semiconductor substrate 1 existing on an insulating film 2, a gate conductor layer 16a connected to a plate line PL, a gate insulating layer 4b formed on the semiconductor substrate, and a second gate conductor layer 5b connected to a word line WL and having a work function different from a work function of the gate conductor layer 16a are disposed on the semiconductor substrate, and data hold operation of holding, near a gate insulating film, holes generated by an impact ionization phenomenon or gate-induced drain leakage current inside a channel region 12 of the semiconductor substrate 1 and data erase operation of removing the holes from inside the substrate 1 and the channel region 12 are performed by controlling voltage applied to the source line SL, the plate line PL, the word line WL, and the bit line BL.

Abstract: A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. A continuous operation of a page erase operation and a page write operation is performed by controlling voltages applied to the source line, the bit line, the word line, and the plate line without performing a reset operation for returning the voltage applied to the plate line to a ground voltage.

Abstract: A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions at both ends of the semiconductor base, and first and second gate conductor layers. A page erase operation, a page write operation, and a page read operation are performed by controlling voltages applied to the first and second impurity regions and the first and second gate conductor layers. In a first page group including at least one page, a refresh operation of increasing positive holes is performed in a memory cell storing logical data “1”. The refresh operation is performed continuously to an N-th page group.

Abstract: A dynamic flash memory includes a p layer as a semiconductor base material, first and second n+ layers on opposite sides thereof, first and second gate insulating layers in contact with each other and partially covering the p layer, and first and second gate conductor layers electrically isolated from each other and respectively provided on the first and second gate insulating layers. The first and second n+ layers and first and second gate conductor layers are respectively connected to source, bit, word, and plate lines. During writing, 1.0 V, 1.5 V, and 1.2 V are sequentially applied to the bit, plate, and word lines, respectively. During erasing, 2 V is applied to the plate line, and then, a voltage applied to each terminal is always set 0 V or greater (e.g., 0.6 V for the bit line). Further, during reading, voltages are sequentially applied to the bit, plate, and word lines.

Abstract: A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction in plan view on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, and in a page read operation, a first refresh operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a second refresh operation of decreasing the number of positive holes in the semiconductor body of a memory cell for which page writing has not been performed are performed and a third refresh operation for a memory cell, in a page, in which the logical “1” data is stored is performed by using latch data in a sense amplifier circuit.

Abstract: A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and a page read operation includes a first refresh operation of increasing by an impact ionization phenomenon, a group of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a subsequent second refresh operation of making some of a group of positive holes in the semiconductor body of a memory cell for which page writing has not been performed disappear and decreasing the number of positive holes.

Abstract: A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and voltages applied to these lines are controlled to perform an erase operation of collecting a group of positive holes in the semiconductor body of a selected memory cell in a part adjacent to the first gate conductor layer and making some of the group of positive holes disappear and a page write operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a selected memory cell in a page.

Abstract: A memory device includes pages each including memory cells arranged in columns in plan view on a substrate, and voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes, generated by an impact ionization phenomenon, inside a semiconductor body. The first and second impurity regions are connected to source and bit lines, the first and second gate conductor layers are connected to word and plate lines, and voltages applied to these lines are controlled to perform a page write operation, a page erase operation, and a page read operation. In the page write operation, the group of positive holes are retained inside the semiconductor body at a first time, and a page write post-processing operation of making a group of excess positive holes disappear is performed at a second time.

Abstract: A dynamic flash memory includes a p layer as a semiconductor base material; first and second n+ layers extending on opposite sides thereof; a first gate insulating layer partially covering the p layer; a first gate conductor layer provided thereon; a second gate insulating layer provided in contact with the first gate insulating layer and partially covering the p layer; and a second gate conductor layer provided on the second gate insulating layer and electrically isolated from the first gate conductor layer. The first and second n+ layers, and the first and second gate conductor layers are respectively connected to a source line, a bit line, a word line, and a plate line. A voltage applied to each terminal during memory erasing is always greater than or equal to 0 V such that 2 V and 0.6 V are respectively applied to the plate line and the bit line.

Abstract: A first semiconductor layer 1 is formed on a substrate, a first impurity layer 3 and a second impurity layer 4 extending in a vertical direction are sequentially disposed on part of the first semiconductor layer 1, their sidewalls and the semiconductor layer 1 are covered by a second gate insulating layer 2, a gate conductor layer 22 and a second insulating layer are disposed in a groove formed there, and a second semiconductor layer 7, n+ layers 6a and 6c positioned at respective ends of the layer 7 and connected to a source line SL and a bit line BL, respectively, a second gate insulating layer 8 formed to cover the second semiconductor layer 7, and a second gate conductor layer 9 connected to a word line WL are disposed on the second impurity layer.

Abstract: A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer and an n layer are provided on respective sides of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a control line, a word line, a plate line, and a source line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.

Abstract: A p layer is a semiconductor base material. An n+ layer is disposed on one extension side. An n+ layer is disposed on the opposite side in contact with the p layer. A gate insulating layer partially covers the p layer. A first gate conductor layer contacts the insulating layer. A second gate conductor layer is electrically separated from the first gate conductor layer. Memory operation is performed by applying voltage to each of the layers. In the operation, the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area is larger than the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area.

Abstract: A p layer is a semiconductor base material. An n+ layer is disposed on one extension side of the layer. An n+ layer is disposed on the opposite side in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in electrical separation from the layer. Memory operation is performed by applying voltage to each of the layers. In this case, the gate capacitance of a MOS structure constituted by the layers per unit area is smaller than that of a MOS structure constituted by the layers.

Abstract: A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer is provided on one side of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a source line, a word line, and a plate line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.

Abstract: A first insulating layer 21 is disposed on a substrate 20. N+ layers 2 are separated from the insulating layer and in directions horizontal and vertical to the substrate. P layers 1 contact the n+ layers 2 and extend in the horizontal direction. N+ layers 3 contact the p layers 1. Gate insulating layers 4 cover the p layers 1 and part of the n+ layers 2 and 3. Second gate conductor layers 6 are electrically separated from a first gate conductor layer 5 contacting the gate insulating layers 4. A conductor layer 12 contacts the n+ layers 2. A conductor layer 13 contacts the n+ layers 3. A second insulating layer 22 contacts the first gate conductor layer 5, the n+ layers 2, and the conductor layer 12. A third insulating layer 23 contacts the second gate conductor layers 6, the n+ layers 3, and the conductor layer 13.

Abstract: A memory device includes pages each including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell are controlled to retain a group of positive holes. In a page write operation, a voltage of the channel semiconductor layer is made equal to a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the voltage of the channel semiconductor layer is made equal to a second data retention voltage, and erase and ground voltages are applied to selected and non-selected pages respectively. The first and second impurity layers and first and second gate conductor layers are connected to source, bit, plate, and word lines. The source, word, and plate lines are disposed parallel to the pages. The bit line is disposed perpendicular to the pages.

Abstract: Si bodies 24aa to 24ad, 24ba to 24bd, and 45a to 45d are disposed parallel to a substrate 20 and are adjacent to each other in a horizontal direction at regular intervals. A HfO2 layer 27b surrounds the Si bodies 24aa to 45d. TiN layers 34a to 34d surround the HfO2 layer 27b, are isolated from each other, and are each formed of portions contiguous in the horizontal direction. The Si bodies 45a to 45d are formed stepwise in cross-sectional view in the terminating end in the horizontal direction. Metal wiring layers 52a to 52d are connected to the TiN layers 34a to 34d and extend up to above an insulating layer 50 through contact holes 51a to 51d extending in a vertical direction from the terminating ends of the TiN layers 34a to 34d. The metal wiring layers 52a to 52d are connected to word lines WL1 to WL4.

Abstract: Provided on a substrate are a first insulating layer; a first metal wire layer embedded therein; a second metal wire layer extending vertically on the first metal wire layer; a first n+ layer on the second metal wire layer, a semiconductor p layer on the first n+ layer, and a second n+ layer on the semiconductor p layer, each extending vertically; a gate insulating layer partially covering them; first and second electrically isolated gate conductor layers around the gate insulating layer; a second insulating layer partially covering the first and second n+ layers and the first and second gate conductor layers; a third insulating layer on the second insulating layer, partially covering the second n+ layer and the second gate conductor layer; and a fourth metal wire layer connecting to the second n+ layer via a contact hole. A fifth metal wire layer connects to the second gate conductor layer.

Abstract: A dynamic flash memory cell and a fin transistor are formed on a P layer substrate 10a. The dynamic flash memory cell includes a first insulating layer 11a, a fin P layer 25, N+ layers 35ba and 35bb, a gate insulating layer 27b, and gate conductor layers 30ba and 30bb; the fin transistor includes a fin P layer 22 including fin P layers 15a and 15b, N+ layers 35aa and 35ab, a gate insulating layer 27a, and a gate conductor layer 30a; in a perpendicular direction, a top portion of the fin P layer 25 is positioned close to or higher than a top portion of the fin P layer 15a, bottom portions of the gate insulating layers 27a and 27b are positioned close to each other, and a bottom portion of the fin semiconductor layer 15b is positioned within the P layer substrate 10a.

Abstract: On a substrate, a first semiconductor layer 1 is formed; from a portion of the layer 1, a first impurity layer 3 extends vertically, and a second semiconductor layer 4 is disposed on the layer 3; side walls of the layers 3 and 4 and the layer 1 are covered with a first gate insulating layer 2; in the resultant grooves, a first gate conductor layer 22 and a second insulating layer 6 are disposed; over the second semiconductor layer 4, layers are disposed that are a third semiconductor layer 8, an n+ layer 7a connecting to a source line SL and an n+ layer 7b connecting to a bit line BL that are disposed on both sides of the layer 8, a second gate insulating layer 9 formed so as to cover the layer 8, and a second gate conductor layer 10 connecting to a word line WL.