Abstract: A semiconductor device may include: a semiconductor layer; and a trench gate. The semiconductor layer may include: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type provided above the first semiconductor region and facing a side surface of the trench gate; and a third semiconductor region of the first conductive type provided above the second semiconductor region, separated from the first semiconductor region by the second semiconductor region, and facing the side surface of the trench gate. The first semiconductor region may include: a lower semiconductor region; and an upper semiconductor region disposed between the lower semiconductor region and the second semiconductor region and having a lower impurity concentration than the lower semiconductor region. The upper semiconductor region may be disposed at a shallower position than the trench gate and face the side surface of the trench gate.

Abstract: A semiconductor device may include: a semiconductor layer; and a trench gate. The semiconductor layer may include: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type provided above the first semiconductor region and facing a side surface of the trench gate; and a third semiconductor region of the first conductive type provided above the second semiconductor region, separated from the first semiconductor region by the second semiconductor region, and facing the side surface of the trench gate. The first semiconductor region may include: a lower semiconductor region; and an upper semiconductor region disposed between the lower semiconductor region and the second semiconductor region and having a lower impurity concentration than the lower semiconductor region. The upper semiconductor region may be disposed at a shallower position than the trench gate and face the side surface of the trench gate.

Abstract: A semiconductor device may include a nitride semiconductor layer, an insulation gate section, and a heterojunction region, wherein the nitride semiconductor layer may include an n-type vertical drift region, a p-type channel region adjoining the vertical drift region, and an n-type source region separated from the vertical drift region by the channel region, wherein the insulation gate section is opposed to a portion of the channel region that separates the vertical drift region and the source region, the heterojunction region is in contact with at least a part of a portion of the vertical drift region that is disposed at the one of main surfaces, and the heterojunction region is an n-type nitride semiconductor or an i-type nitride semiconductor having a bandgap wider than a bandgap of the vertical drift region.

Abstract: A semiconductor device is capable of accurately sensing a temperature of a semiconductor element incorporated in a semiconductor substrate. The semiconductor device includes a temperature sensor. The temperature sensor includes a first nitride semiconductor layer of p-type, a first sense electrode, and a second sense electrode. The first sense electrode and the second sense electrode are located to be capable of passing an electric current between the first sense electrode and the second sense electrode through the first nitride semiconductor layer.

Abstract: A semiconductor device may include a nitride semiconductor layer, an insulation gate section, and a heterojunction region, wherein the nitride semiconductor layer may include an n-type vertical drift region, a p-type channel region adjoining the vertical drift region, and an n-type source region separated from the vertical drift region by the channel region, wherein the insulation gate section is opposed to a portion of the channel region that separates the vertical drift region and the source region, the heterojunction region is in contact with at least a part of a portion of the vertical drift region that is disposed at the one of main surfaces, and the heterojunction region is an n-type nitride semiconductor or an i-type nitride semiconductor having a bandgap wider than a bandgap of the vertical drift region.

Abstract: A semiconductor device includes: an electron transit layer constituted of GaN; an electron supply layer constituted of Inx1Aly1Ga1?x1?y1N (0?x1<1, 0?y1<1, 0<1?x1?y1<1) and provided on the electron transit layer; a source electrode and a drain electrode that are provided on the electron supply layer and located apart from each other; a threshold voltage adjustment layer constituted of Inx2Aly2Ga1?x2?y2N (0?x2<1, 0?y2<1, 0<1?x2?y2?1) of a p-type and provided on a part of the electron supply layer located between the source electrode and the drain electrode; and a gate electrode provided on the threshold voltage adjustment layer. A high resistance layer is respectively interposed both between the gate electrode and the threshold voltage adjustment layer, and between the threshold voltage adjustment layer and the electron supply layer.

Abstract: A nitride semiconductor device includes a conductive substrate and a nitride semiconductor layer. The nitride semiconductor layer is disposed on the conductive substrate. The nitride semiconductor layer includes a first transistor structure of a lateral type and a second transistor structure of a lateral type. The conductive substrate includes a first potential control region and a second potential control region capable of controlling potential independently from the first potential control region. In planar view of the nitride semiconductor layer, the first transistor structure overlaps the first potential control region and the second transistor structure overlaps the second potential control region.

Abstract: A nitride semiconductor device includes a conductive substrate and a nitride semiconductor layer. The nitride semiconductor layer is disposed on the conductive substrate. The nitride semiconductor layer includes a first transistor structure of a lateral type and a second transistor structure of a lateral type. The conductive substrate includes a first potential control region and a second potential control region capable of controlling potential independently from the first potential control region. In planar view of the nitride semiconductor layer, the first transistor structure overlaps the first potential control region and the second transistor structure overlaps the second potential control region.

Abstract: A semiconductor device includes: an electron transit layer constituted of GaN; an electron supply layer constituted of Inx1Aly1Ga1-x1-y1N (0?x1<1, 0?y1<1, 0<1?x1?y1<1) and provided on the electron transit layer; a source electrode and a drain electrode that are provided on the electron supply layer and located apart from each other; a threshold voltage adjustment layer constituted of Inx2Aly2Ga1-x2-y2N (0?x2<1, 0?y2<1, 0<1?x2?y2?1) of a p-type and provided on a part of the electron supply layer located between the source electrode and the drain electrode; and a gate electrode provided on the threshold voltage adjustment layer. A high resistance layer is respectively interposed both between the gate electrode and the threshold voltage adjustment layer, and between the threshold voltage adjustment layer and the electron supply layer.

Abstract: Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode.

Abstract: A semiconductor device is capable of accurately sensing a temperature of a semiconductor element incorporated in a semiconductor substrate. The semiconductor device includes a temperature sensor. The temperature sensor includes a first nitride semiconductor layer of p-type, a first sense electrode, and a second sense electrode. The first sense electrode and the second sense electrode are located to be capable of passing an electric current between the first sense electrode and the second sense electrode through the first nitride semiconductor layer.

Abstract: Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode.

Abstract: A switching device provided herewith includes first to fourth semiconductor layers and a gate electrode. The second semiconductor layer is of a first conductive type or an un-dope type and located on the first semiconductor layer. A hetero junction is formed between the first and the second semiconductor layers. The third semiconductor layer is of a second conductive type and located on the second semiconductor layer. The fourth semiconductor layer is of a second conductive type and located on the third semiconductor layer. A hetero junction is formed between the third and the fourth semiconductor layers. The gate electrode electrically connected to the fourth semiconductor layer.

Abstract: A semiconductor device includes a hetero junction structure including an electron transport layer of GaN and an electron supply layer of Inx1Aly1Ga1-x1-y1N (0?x1?1, 0?y1?1, 0?1?x1?y1<1), source and drain electrodes provided above an surface of the electron supply layer, a p-type layer of Inx2Aly2Ga1-x2-y2N (0?x2?1, 0?y2?1, 0?1?x2?y2?1) provided above the surface of the electron supply layer and between the source electrode and the drain electrode, a gate electrode provided to be electrical contact with the p-type layer, and an insulation layer covering at least one of the surface of the electron supply layer exposed between the source electrode and the p-type layer and the surface of the electron supply layer exposed between the drain electrode and the p-type layer, wherein positive charges are fixed in at least a part of the insulation layer.

Abstract: A semiconductor device includes a first compound semiconductor layer, a second compound semiconductor layer having a larger band gap than that of the first compound semiconductor layer, p-type third compound semiconductor layer disposed above a portion of the second compound semiconductor layer, a p-type fourth compound semiconductor layer disposed above the third compound semiconductor layer and having a higher resistance than that of the third compound semiconductor layer, and a gate electrode disposed above the fourth compound semiconductor layer.

Abstract: Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode.

Abstract: An SBD is obtained by forming, on a front surface of a substrate in which a first nitride semiconductor layer and a second nitride semiconductor layer are laminated, an anode electrode configured to make Schottky contact and a cathode electrode configured to make Ohmic contact. The anode electrode is made to have a mixture of a portion that is in direct contact with the second nitride semiconductor layer and a portion that is in contact with the second nitride semiconductor layer via a fourth nitride semiconductor layer and a third nitride semiconductor layer. Using a p-type nitride semiconductor as the fourth layer makes it possible to suppress the leakage current. Using, as the third layer, a nitride semiconductor that is wider in band gap than the second nitride semiconductor layer makes it possible to keep down the lowest value of forward voltage at which a forward current flows.

Abstract: A switching device provided herewith includes first to fourth semiconductor layers and a gate electrode. The second semiconductor layer is of a first conductive type or an un-dope type and located on the first semiconductor layer. A hetero junction is formed between the first and the second semiconductor layers. The third semiconductor layer is of a second conductive type and located on the second semiconductor layer. The fourth semiconductor layer is of a second conductive type and located on the third semiconductor layer. A hetero junction is formed between the third and the fourth semiconductor layers. The gate electrode electrically connected to the fourth semiconductor layer.

Abstract: A nitride semiconductor device 2 comprises a nitride semiconductor layer 10. A gate insulating film 16 is formed on the surface of the nitride semiconductor layer 10. The gate insulating film 16 includes a portion composed of an aluminum nitride film 15 and a portion composed of an insulating material 14 that contains at least one of oxygen or silicon. A region W2 of the nitride semiconductor layer 10 facing the aluminum nitride film 15 is included in a region W1 of the nitride semiconductor layer 10 facing a gate electrode 18. The nitride semiconductor device 2 may further comprise a nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may be stacked on the surface of the nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may have a larger band gap than that of the nitride semiconductor lower layer 8 and have a heterojunction formed there between.

Abstract: A semiconductor device has a semiconductor substrate having a surface layer and a p-type semiconductor region, wherein the surface layer includes a contact region, a channel region and a drift region, the channel region is adjacent to and in contact with the contact region, the drift region is adjacent to and in contact with the channel region and includes n-type impurities at least in part, and the p-type semiconductor region is in contact with the drift region and at least a portion of a rear surface of the channel region, a main electrode disposed on the surface layer and electrically connected to the contact region, a gate electrode disposed on the surface layer and extending from above a portion of the contact region to above at least a portion of the drift region via above the channel region, and an insulating layer covering at least the portion of the contact region and not covering at least the portion of the drift region.