Abstract: A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Abstract: In a semiconductor memory device in which each memory cell is constituted by one transistor, in a memory cell pattern, two adjacent bits form one diffusion pattern, two adjacent transistors share a source region, and two drain regions are separated from each other. A plurality of arrays in each of which at least a column of the diffusion patterns is disposed include bit lines, and the bit lines of the first array are independent of the bit lines of the second array. In an interface between the arrays, ends at one side of the bit lines of each of the arrays are located on an associated one of two drain regions which are separated from each other with the source region which is shared on one diffusion pattern sandwiched therebetween. This configuration can provide a sufficient bit-line separation width, and reduce the area.

Abstract: A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Abstract: In a semiconductor memory device in which each memory cell is constituted by one transistor, in a memory cell pattern, two adjacent bits form one diffusion pattern, two adjacent transistors share a source region, and two drain regions are separated from each other. A plurality of arrays in each of which at least a column of the diffusion patterns is disposed include bit lines, and the bit lines of the first array are independent of the bit lines of the second array. In an interface between the arrays, ends at one side of the bit lines of each of the arrays are located on an associated one of two drain regions which are separated from each other with the source region which is shared on one diffusion pattern sandwiched therebetween. This configuration can provide a sufficient bit-line separation width, and reduce the area.

Abstract: In a pump device applicable to a power steering apparatus, a pump element is housed within a pump housing and is configured to drain a working oil, an electric motor is configured to drive the pump element, a reservoir tank is installed on the housing and is configured to reserve the working oil supplied to the oil element, a passage is formed within the pump housing and is connected to the pump element, and a control valve is installed in the pump housing, is configured to communicate with the passage, and is configured to control a flow of the working oil caused to flow through the passage.

Abstract: An oil pump including a first housing having a rotation shaft insertion hole, a cam ring, a pump element, a rotation shaft rotatably extending through the rotation shaft insertion hole, a second housing disposed on the cam ring, wherein the cam ring is placed in a position relative to the rotation shaft insertion hole of the first housing by using a jig, and the cam ring includes a clamped portion that is clamped by a cam ring holding device, while the first housing and the second housing are fixed to each other after placing the cam ring in the position relative to the rotation shaft insertion hole by using the jig. Alternatively, the oil pump including a fixing means for fixing the cam ring to the pump body instead of the clamped portion.

Abstract: An internal gear pump has a first port opening into pumping chambers and provided at one side with respect to a first axis interconnecting a confinement portion of the pumping chambers having a maximum volumetric capacity and a deeply-meshed-engagement portion of the pumping chambers having a minimum volumetric capacity, a second port opening into the pumping chambers and provided at the opposite side with respect to the first axis, a first pressure introduction passage intercommunicating the first port and a first-port side area of a clearance space defined on an outer periphery of an outer rotor, and a second pressure introduction passage intercommunicating the second port and a second-port side area of the clearance space. The clearance space of a direction of a second axis perpendicular to the first axis is dimensioned to be greater than the clearance space of a direction of the first axis.

Abstract: In order to realize cost reduction in a gear pump apparatus by reducing form accuracy of a gear while securing pump performance, a running-in coating is provided on a tooth sliding contact portion when forming a confinement area in at least one of gears of the gear pump apparatus. By this feature, the running-in coating is gradually worn away and deformed according to rotary drive of the pump, and thus it is possible to obtain an optimal gear form in meshing combinations of the gears. Further, it is possible to reduce leakage inside the pump to secure the pump performance even if the form accuracy of the gear is reduced for the sake of the cost reduction.

Abstract: A power steering system includes a hydraulic power cylinder having a first and a second hydraulic chambers, for assisting a steering force of a steering mechanism, a first and a second oil passages respectively connected to the first and second hydraulic chambers, a reversible pump discharging operating oil and providing oil pressure to the hydraulic power cylinder through the first and second oil passages, and a motor connected to the reversible pump and rotating the reversible pump in normal and reverse directions. A steering load detection unit detects a steering load of a steering wheel for steering of the steered road wheels, and a motor control unit outputs a control signal to the motor to bring an actual oil pressure generated by the reversible pump closer to a desired oil pressure determined based on the detected steering load. A discharge amount per rotation of the reversible pump is smaller than or equal to 5 cc.

Abstract: In a conventional semiconductor memory device, a replica circuit configured by using a dummy bit line has been unable to charge the dummy bit line to a desired potential due to off leak current. Consequently, the time required for charging or discharging the dummy bit line differs from the desired time, and therefore, it has been unable to set optimum operation timing. To solve these problems, a semiconductor memory device of the present invention includes a dummy memory cell array in which source lines of dummy memory cells are charged simultaneously by a charge circuit configured similarly to a dummy bit line charge circuit, thus suppressing off leak current and performing appropriate timing generation.

Abstract: A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Abstract: A power steering apparatus includes a power cylinder; a reversible pump; first and second hydraulic passages; a reservoir tank; a first supply passage arranged to supply the hydraulic fluid through the reversible pump to the second hydraulic passage; a first one-way valve provided in the first supply passage; a second supply passage arranged to supply the hydraulic fluid through the reversible pump to the first hydraulic passage; and a second one-way valve provided in the second supply passage. A Reynolds number of a flow in the first one-way valve is equal to or smaller than 2300 when a flow rate per unit time of the flow in the first one-way valve is maximum. A Reynolds number of a flow in the second one-way valve is equal to or smaller than 2300 when a flow rate per unit time of the flow in the second one-way valve is maximum.

Abstract: In an oil pump employing a cam ring, and inner and outer rotors in meshed-engagement, two housings are provided at opposite ends of the cam ring. A plurality of volume chambers are defined between inner and outer teeth of the rotors. Two axial holes are formed in the cam ring. A first one of the axial holes is positioned corresponding to a mesh portion having a minimum volume, whereas the second axial hole is positioned corresponding to a trap portion having a maximum volume. A suction port and a discharge port are formed at least in one of the housings and are open to the volume chambers between the mesh and trap portions. All are positioned at a line symmetry of an axis line between the mesh and trap portions. At least one of the two axial holes is formed as a slot extending along the axis lines.

Abstract: A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

Abstract: An oil pump including a first housing having a rotation shaft insertion hole, a cam ring, a pump element, a rotation shaft rotatably extending through the rotation shaft insertion hole, a second housing disposed on the cam ring, wherein the cam ring is placed in a position relative to the rotation shaft insertion hole of the first housing by using a jig, and the cam ring includes a clamped portion that is clamped by a cam ring holding device, while the first housing and the second housing are fixed to each other after placing the cam ring in the position relative to the rotation shaft insertion hole by using the jig. Alternatively, the oil pump including a fixing means for fixing the cam ring to the pump body instead of the clamped portion.

Abstract: A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

Abstract: A first fluid passage extends from a first outlet/inlet port of a hydraulic pump to a first work chamber of a power cylinder, and a second fluid passage extends from a second outlet/inlet port of the pump to a second work chamber of the power cylinder. A switch system switches the role of the first and second outlet/inlet ports in accordance with a turning direction of a steering wheel. Flow control mechanisms are respectively incorporated with the first and second fluid passages, so that a controlled flow of hydraulic fluid from the hydraulic pump to the first or second work chamber and vice versa are appropriately carried out thereby providing the driver with a comfortable steering feeling. A bypass arrangement may be provided between the first and second fluid passages to deal with a residual pressure that would be remained in the first or second work chamber when the hydraulic pump is under inoperative condition.

Abstract: An internal gear pump has a first port opening into pumping chambers and provided at one side with respect to a first axis interconnecting a confinement portion of the pumping chambers having a maximum volumetric capacity and a deeply-meshed-engagement portion of the pumping chambers having a minimum volumetric capacity, a second port opening into the pumping chambers and provided at the opposite side with respect to the first axis, a first pressure introduction passage intercommunicating the first port and a first-port side area of a clearance space defined on an outer periphery of an outer rotor, and a second pressure introduction passage intercommunicating the second port and a second-port side area of the clearance space. The clearance space of a direction of a second axis perpendicular to the first axis is dimensioned to be greater than the clearance space of a direction of the first axis.

Abstract: In order to realize cost reduction in a gear pump apparatus by reducing form accuracy of a gear while securing pump performance, a running-in coating is provided on a tooth sliding contact portion when forming a confinement area in at least one of gears of the gear pump apparatus. By this feature, the running-in coating is gradually worn away and deformed according to rotary drive of the pump, and thus it is possible to obtain an optimal gear form in meshing combinations of the gears. Further, it is possible to reduce leakage inside the pump to secure the pump performance even if the form accuracy of the gear is reduced for the sake of the cost reduction.

Abstract: In a conventional semiconductor memory device, a replica circuit configured by using a dummy bit line has been unable to charge the dummy bit line to a desired potential due to off leak current. Consequently, the time required for charging or discharging the dummy bit line differs from the desired time, and therefore, it has been unable to set optimum operation timing. To solve these problems, a semiconductor memory device of the present invention includes a dummy memory cell array in which source lines of dummy memory cells are charged simultaneously by a charge circuit configured similarly to a dummy bit line charge circuit, thus suppressing off leak current and performing appropriate timing generation.