Abstract: An ADC test circuit has an expected value generator configured to generate an expected value signal for a converted output signal of an ADC (Analog to Digital Converter), a test signal generator configured to generate an input test signal applied to the ADC based on the expected value signal, and a comparator configured to compare the converted output signal of the ADC corresponding to the applied input test signal with the expected value signal.

Abstract: A control system comprises an interrupt controller, having vector access signal output mechanism for outputting a vector access signal, which is activated when a start address is read out from a vector holder, and a central processing unit (CPU), comprising a present mask holder, which holds a present mask level, and a previous mask holder, which holds a previous mask level, wherein the CPU compares the interrupt level and the present mask level, and, when the interrupt level is higher than the present mask level, copies a value of the present mask level holder into the previous mask level holder, reads out a start address of an interrupt processing program corresponding to an accepted interrupt request from the vector holder, starts executing the interrupt processing program, and copies the interrupt level into a present mask level holder by means of an activated vector access signal.