Patents by Inventor Masakazu Nakabayashi
Masakazu Nakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040178477Abstract: A semiconductor wafer is provided, where the crossing angle (&thgr;) between an inclined surface and a first main surface ranges from 8 to 15 degrees. Similarly, the crossing angle (&thgr;) between an inclined surface and a second main surface ranges from 8 to 15 degrees. Further, the chamfer width of the inclined surfaces is 200 micrometers. This configuration optimizes the shape of the circumferential end face portion of a semiconductor wafer, such that a semiconductor wafer can be provided with improved yield of semiconductor devices formed on a semiconductor wafer.Type: ApplicationFiled: September 3, 2003Publication date: September 16, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventor: Masakazu Nakabayashi
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Patent number: 6784471Abstract: A semiconductor device capable of reducing manufacturing cost and on-state resistance is provided by selectively disposing a plurality of active regions (AR) on a main surface of a stainless steel substrate (1) and disposing a trench gate (7) so as to bury the area between the active regions (AR). The active regions (AR) have a multilayer structure that is made up of a drain layer (2) containing antimony (Sb) as an n-type impurity in a relatively high concentration (n+), a polysilicon layer (3) overlying the drain layer (2) and containing a p-type impurity, and a source layer (4) overlying the polysilicon layer (3) and containing an n-type impurity in a relatively high concentration (n+).Type: GrantFiled: May 22, 2002Date of Patent: August 31, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masakazu Nakabayashi
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Patent number: 6753573Abstract: A P-well region and an N-well region are formed in an upper layer of a silicon wafer. A shallow trench having a depth of 0.05 &mgr;m to 0.1 &mgr;m is formed in the vicinity of a boundary between the P-well region and the N-well region. A gate oxide film is formed on an entire surface of the silicon wafer. On a bottom of the shallow trench of the P-well region and the outer layer of the silicon wafer contacting the upper ends of the sidewall of the shallow trench are formed n+-diffusion layers. On the bottom of the shallow trench of the N-well region and the outer layer of the silicon wafer contacting the upper ends of the sidewall of the shallow trench are formed p+-diffusion layers. On the sidewalls of the shallow trench, gate electrodes are formed through the gate oxide film. A silicon oxide film is formed so as to cover the gate electrodes. Electrodes contacting the diffusion layers are formed through the silicon oxide film.Type: GrantFiled: March 18, 2003Date of Patent: June 22, 2004Assignee: Renesas Technology Corp.Inventor: Masakazu Nakabayashi
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Patent number: 6738484Abstract: A pressure responsive device capable of achieving thinning or miniaturization while maintaining a high performance and a method of manufacturing a semiconductor substrate for use therein. A back electrode is placed on a bottom surface of a concave formed on a central portion of a main surface of a semiconductor substrate. A peripheral edge portion of a vibrating electrode membrane is fixed on a peripheral surface surrounding the concave. In this manner, a capacitor including the back electrode/a space (air)/the vibrating electrode membrane is formed. The concave is formed by etching, and therefore a variation in depth of the concave in each apparatus is suppressed. As a result, a highly reliable and inexpensive pressure responsive apparatus is obtained.Type: GrantFiled: October 4, 2001Date of Patent: May 18, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masakazu Nakabayashi
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Publication number: 20040084723Abstract: A P-well region and an N-well region are formed in an upper layer of a silicon wafer. A shallow trench having a depth of 0.05 &mgr;m to 0.1 &mgr;m is formed in the vicinity of a boundary between the P-well region and the N-well region. A gate oxide film is formed on an entire surface of the silicon wafer. On a bottom of the shallow trench of the P-well region and the outer layer of the silicon wafer contacting the upper ends of the sidewall of the shallow trench are formed n+-diffusion layers. On the bottom of the shallow trench of the N-well region and the outer layer of the silicon wafer contacting the upper ends of the sidewall of the shallow trench are formed p+-diffusion layers. On the sidewalls of the shallow trench, gate electrodes are formed through the gate oxide film. A silicon oxide film is formed so as to cover the gate electrodes. Electrodes contacting the diffusion layers are formed through the silicon oxide film.Type: ApplicationFiled: March 18, 2003Publication date: May 6, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Masakazu Nakabayashi
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Publication number: 20030115177Abstract: A process failure information management system including a server and a terminal, in which an user inputs information concerning a process failure using the terminal and the input information are stored into a database of the server. The date of input by the user is stored into the database. When a prescribed period has passed from the date of input stored in the database without input by an user of the following step, the server sends an E-mail for asking for an input of information to the user who inputs information at the following step.Type: ApplicationFiled: June 14, 2002Publication date: June 19, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Naoko Takanabe, Saori Kakei, Masakazu Nakabayashi, Masahiko Morishita, Akira Hamasaki, Shoko Kanazawa
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Patent number: 6568269Abstract: The invention provides a highly reliable acceleration sensor capable of being manufactured at a low cost easily, and a manufacturing method the acceleration sensor. The acceleration sensor comprises: a fixed electrode (50, a movable electrode (40), and a mass member (30) joined to the movable electrode (40) and displaceable. The mass member (30) is mainly constructed of a thin polyimide membrane (2). Therefore the acceleration sensor can be manufactured in a shorter period of time and more easily as compared with a conventional construction utilizing a polysilicon membrane, and a shorter manufacturing time and lower cost is achieved.Type: GrantFiled: November 2, 2001Date of Patent: May 27, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masakazu Nakabayashi
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Patent number: 6564422Abstract: A vacuum cleaner is provided which has a simple structure and exerts suction without involving discharge of gas at all so that it can be used in extremely clean environments. A vacuum cleaner (100) comprises a vacuum tank (1) which is previously evacuated to create a vacuum inside, a valve (2) for keeping the vacuum tank 1 airtight, and a suction unit (20) attached to the valve (2); the valve (2) is opened when the vacuum cleaner (100) is used. The valve (2) is a so-called gate valve and the vacuum tank (1) is kept airtight when the gate valve element (22) in the valve (2) is closed. A connection inlet (23) is attached to the valve (2) on the side opposite to its surface attached to the vacuum tank (1). A connection adapter (31) is screwed into the connection inlet (23) and an attachment, e.g. a flexible suction hose (32), is attached to the connection adapter (31).Type: GrantFiled: October 12, 2001Date of Patent: May 20, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masakazu Nakabayashi
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Publication number: 20030032249Abstract: A semiconductor device capable of reducing manufacturing cost and on-state resistance is provided by selectively disposing a plurality of active regions (AR) on a main surface of a stainless steel substrate (1) and disposing a trench gate (7) so as to bury the area between the active regions (AR). The active regions (AR) have a multilayer structure that is made up of a drain layer (2) containing antimony (Sb) as an n-type impurity in a relatively high concentration (n+), a polysilicon layer (3) overlying the drain layer (2) and containing a p-type impurity, and a source layer (4) overlying the polysilicon layer (3) and containing an n-type impurity in a relatively high concentration (n+).Type: ApplicationFiled: May 22, 2002Publication date: February 13, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Masakazu Nakabayashi
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Patent number: 6500683Abstract: A method of directly measuring a trench depth without damages to a wafer is provided. First, the focus of a lens (LZ) of a microscope is adjusted so that a tip (TP) of a projection (PP) of a negative replica (NR) is plainly visible through the microscope, and a vertical position (A) of a stage (ST) at that time is identified. Next, with the lens (LZ) held at the same position, the stage (ST) is gradually moved toward the lens (LZ) and is stopped moving at a position where a surface (SF) of a base (BP) of the negative replica (NR) is plainly visible through the microscope. A vertical position (B) of the stage (ST) at that time is identified. Then, a difference between the vertical position (B) and the vertical position (A) is obtained to determine a distance (MD) moved, i.e., the height of the projection (PP).Type: GrantFiled: April 11, 2002Date of Patent: December 31, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masakazu Nakabayashi, Tadayuki Yoshiyama
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Publication number: 20020189047Abstract: A vacuum cleaner is provided which has a simple structure and exerts suction without involving discharge of gas at all so that it can be used in extremely clean environments. A vacuum cleaner (100) comprises a vacuum tank (1) which is previously evacuated to create a vacuum inside, a valve (2) for keeping the vacuum tank 1 airtight, and a suction unit (20) attached to the valve (2); the valve (2) is opened when the vacuum cleaner (100) is used. The valve (2) is a so-called gate valve and the vacuum tank (1) is kept airtight when the gate valve element (22) in the valve (2) is closed. A connection inlet (23) is attached to the valve (2) on the side opposite to its surface attached to the vacuum tank (1). A connection adapter (31) is screwed into the connection inlet (23) and an attachment, e.g. a flexible suction hose (32), is attached to the connection adapter (31).Type: ApplicationFiled: October 12, 2001Publication date: December 19, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Masakazu Nakabayashi
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Publication number: 20020178818Abstract: The invention provides a highly reliable acceleration sensor capable of being manufactured at a low cost easily, and a manufacturing method the acceleration sensor. The acceleration sensor comprises: a fixed electrode (50, a movable electrode (40), and a mass member (30) joined to the movable electrode (40) and displaceable. The mass member (30) is mainly constructed of a thin polyimide membrane (2). Therefore the acceleration sensor can be manufactured in a shorter period of time and more easily as compared with a conventional construction utilizing a polysilicon membrane, and a shorter manufacturing time and lower cost is achieved.Type: ApplicationFiled: November 2, 2001Publication date: December 5, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Masakazu Nakabayashi
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Publication number: 20020172382Abstract: The invention provides a pressure responsive device capable of achieving thinning or miniaturization while maintaining a high performance and a method of manufacturing a semiconductor substrate for use therein. A back electrode 5 is placed on a bottom surface 4a of a concave 4 formed on a central portion of a main surface 3a of a semiconductor substrate 3. A peripheral edge portion of a vibrating electrode membrane 7 is fixed on a peripheral surface 3c surrounding the concave 4. In this manner, a capacitor comprised of the back electrode 5/a space 8 (air)/the vibrating electrode membrane 7 is formed. The concave 4 is formed by etching, and therefore variation in depth of the concave 4 in each apparatus is suppressed. As a result, a highly reliable and inexpensive pressure responsive apparatus is obtained.Type: ApplicationFiled: October 4, 2001Publication date: November 21, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Masakazu Nakabayashi
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Patent number: 6461938Abstract: A method of producing semiconductor devices includes bonding one side of an expandable resin wafer sheet with thermosetting adhesive layers on both sides to a back side of a semiconductor wafer, and dividing the semiconductor wafer into semiconductor elements by dicing to form separation grooves; expanding the wafer sheet, widening the separation grooves between the semiconductor elements; positioning one of the semiconductor elements on a die pad of a lead frame to be die-bonded; cutting the wafer sheet opposite the expanded separation grooves surrounding the semiconductor element which has been positioned on the die pad, separating a piece of the wafer sheet with a semiconductor element on the piece of the wafer sheet, and pressing the adhesive surface on the side of the piece of the wafer sheet opposite the semiconductor element onto a surface of the die pad.Type: GrantFiled: December 21, 2000Date of Patent: October 8, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masakazu Nakabayashi
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Patent number: 6383832Abstract: The invention provides a pressure responsive device capable of achieving thinning or miniaturization while maintaining a high performance and a method of manufacturing a semiconductor substrate for use therein. A spacer means (6) made of polyimide is disposed on a semiconductor substrate (3) having a back plate (4), and a peripheral portion of a vibrating electrode membrane (8) is supported by the spacer (6), thereby forming a capacitor comprised of the back plate (4)/a space (9) (air)/the vibrating electrode membrane (8). Additionally, a silicon nitride membrane (7) serving as a flattening membrane is provided on the supporting surface of the spacer means (6) made of polyimide so that variation in thickness of the polyimide membrane in each apparatus is controlled. As a result, fluctuations in performance of each devices are suppressed and a highly reliable pressure responsive apparatus is obtained.Type: GrantFiled: September 21, 2001Date of Patent: May 7, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masakazu Nakabayashi
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Publication number: 20010001078Abstract: Providing a method for die bonding semiconductor elements surely without causing damage thereto in a shorter time with less steps of operations, thereby improving the productivity.Type: ApplicationFiled: December 21, 2000Publication date: May 10, 2001Inventor: Masakazu Nakabayashi
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Patent number: 6215194Abstract: Providing a method for die bonding semiconductor elements surely without causing damage thereto in a shorter time with less steps of operations, thereby improving the productivity.Type: GrantFiled: April 7, 1999Date of Patent: April 10, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masakazu Nakabayashi