Abstract: A full bridge circuit comprises first to fourth magnetic resistance elements. The first and fourth magnetic resistance elements have a first polarity, while the second and third magnetic resistance elements have a second polarity. A comparison circuit compares a first value indicating a difference between a potential of a first connecting node and a first potential and a second value indicating a difference between a potential of a second connecting node and a second potential to determine presence/absence of an external magnetic field. An initial magnetization vector of a magnetization free layer of the first magnetic resistance element is the reverse of that of a magnetization free layer of the second magnetic resistance element. An initial magnetization vector of a magnetization free layer of the third magnetic resistance element is the reverse of that of a magnetization free layer of the fourth magnetic resistance element.

Abstract: According to one embodiment, a signal processing circuit includes: (i) a plurality of input ends to which respective input signals are supplied; (ii) a plurality of signal processing paths that are provided to correspond to the input ends; (iii) a switching circuit that performs switching between connections of the input ends and signal processing paths; (iv) an output circuit that supplies, to one or more output ends, output signals of the signal processing paths in association with the respective input signals that are supplied to the input ends.

Abstract: A semiconductor device according to the present embodiment is provided with a controller, a first detector, a second detector, and a determiner. In a first measurement, the first detector detects a first measured value correlated with the propagation time of the first acoustic wave in a first detection period from the transmission to the reception of the first acoustic wave. In a second measurement, the second detector detects a second measured value correlated with the propagation time of the second acoustic wave in a second detection period from the transmission to the reception of the second acoustic wave. The determiner determines the presence or absence of the second measurement on the basis of the result of comparison between the first measured value and another first measured value measured earlier than the first measured value.

Abstract: A semiconductor device according to the present embodiment is provided with a controller, a first detector, a second detector, and a determiner. In a first measurement, the first detector detects a first measured value correlated with the propagation time of the first acoustic wave in a first detection period from the transmission to the reception of the first acoustic wave. In a second measurement, the second detector detects a second measured value correlated with the propagation time of the second acoustic wave in a second detection period from the transmission to the reception of the second acoustic wave. The determiner determines the presence or absence of the second measurement on the basis of the result of comparison between the first measured value and another first measured value measured earlier than the first measured value.

Abstract: According to one embodiment, there is provided a semiconductor device. The semiconductor device includes a metering unit that operates under control of a first processor to measure electric power consumed, a communication unit that operates under the control of a second processor different from the first processor to perform communication, and a path connecting the metering unit and the communication unit.

Abstract: A full bridge circuit comprises first to fourth magnetic resistance elements. The first and fourth magnetic resistance elements have a first polarity, while the second and third magnetic resistance elements have a second polarity. A comparison circuit compares a first value indicating a difference between a potential of a first connecting node and a first potential and a second value indicating a difference between a potential of a second connecting node and a second potential to determine presence/absence of an external magnetic field. An initial magnetization vector of a magnetization free layer of the first magnetic resistance element is the reverse of that of a magnetization free layer of the second magnetic resistance element. An initial magnetization vector of a magnetization free layer of the third magnetic resistance element is the reverse of that of a magnetization free layer of the fourth magnetic resistance element.

Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.

Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.

Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.

Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.