Patents by Inventor Masakazu Yamashina
Masakazu Yamashina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7366821Abstract: A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing reflection and loads on the bus, a higher data transmission speed can be obtained.Type: GrantFiled: June 20, 2001Date of Patent: April 29, 2008Assignee: NEC CorporationInventors: Muneo Fukaishi, Masato Motomura, Yoshiharu Aimoto, Masakazu Yamashina
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Publication number: 20030163606Abstract: A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing reflection and loads on the bus, a higher data transmission speed can be obtained.Type: ApplicationFiled: March 18, 2003Publication date: August 28, 2003Inventors: Mueo Fukaishi, Masato Motomura, Yoshiharu Aimoto, Masakazu Yamashina
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Patent number: 6229360Abstract: A first latching circuit transferring an input signal from the input terminal to the output terminal for a predetermined period in response to a level transition timing of one direction of a clock signal input to the clock terminal, and maintaining a signal condition of the output terminal in the remaining period, and a second latching circuit transferring an input signal from the input terminal to the output terminal for a predetermined period in response to a level transition timing of the other direction of the clock signal input to the clock terminal, and maintaining a signal condition of the output terminal in the remaining period, are provided. A desired logic circuit is connected between the first and second latching circuits. By synchronously operating the first and second latching circuits by supplying a common clock signal, a clock synchronization circuit not influenced by fluctuation of the device, fluctuation of temperature or power source can be formed.Type: GrantFiled: September 9, 1998Date of Patent: May 8, 2001Assignee: NEC CorporationInventors: Masayuki Mizuno, Masakazu Yamashina
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Patent number: 6094068Abstract: A CMOS logic circuit including (a) a PMOS transistor, (b) an NMOS transistor, (c) a first coupling capacitor electrically connected only between a gate and a substrate of the PMOS transistor, and (d) a second coupling capacitor electrically connected between a gate and drain of the NMOS transistor, wherein the PMOS and NMOS transistors include substrate voltages which are made higher than associated reference voltages during rising edges of signals transmitted to the gates, and made lower than the associated reference voltages during falling edges of the signals. The gates of the PMOS and NMOS transistors are electrically connected to each other, drains of the PMOS and NMOS transistors are electrically connected to each other, and an input signal is introduced into the electrically connected gates, and an output signal is taken through the electrically connected drains.Type: GrantFiled: June 18, 1998Date of Patent: July 25, 2000Assignee: NEC CorporationInventors: Masahiro Nomura, Masakazu Yamashina
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Patent number: 5801570Abstract: A plurality of MOS transistors connected to each other at a substrate electrode thereof to have a substrate potential are deviation-compensated by a combination of a power source having a power source potential independent from the substrate potential, a power supply line connected to a source electrode of each of the MOS transistors, a sample circuit composed of a sampled one of the MOS transistors, detection circuitry for detecting an action of the sample circuit to provide a detection signal representing a difference between the detected action of the sample circuit and a reference action therefor, and a voltage generator connected between the power source and the power supply line, the voltage generator generating a voltage depending on the detection signal.Type: GrantFiled: May 20, 1997Date of Patent: September 1, 1998Assignee: NEC CorporationInventors: Masayuki Mizuno, Masakazu Yamashina
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Patent number: 5742195Abstract: A plurality of MOS transistors connected to each other at a substrate electrode thereof to have a substrate potential are deviation-compensated by a combination of a power source having a power source potential independent from the substrate potential, a power supply line connected to a source electrode of each of the MOS transistors, a sample circuit composed of a sampled one of the MOS transistors, detection circuitry for detecting an action of the sample circuit to provide a detection signal representing a difference between the detected action of the sample circuit and a reference action therefor, and a voltage generator connected between the power source and the power supply line, the voltage generator generating a voltage depending on the detection signal.Type: GrantFiled: February 2, 1996Date of Patent: April 21, 1998Assignee: NEC CorporationInventors: Masayuki Mizuno, Masakazu Yamashina
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Patent number: 5686853Abstract: The present invention provides a driver circuitry having a single input terminal for receiving an input signal of binary digits consisting of high and low levels, and at least first and second output terminals, wherein the input signal is varied almost linearly in a first time period so as to be shifted between high and low levels, the driver circuitry comprises first and second control circuits. The first control circuit is coupled to the input terminal for receiving the input signal. The first control circuit is also coupled to the first output terminal for outputting a first output signal of binary digits via the first output terminal. The first control circuit is biased between a high voltage line which supplies a high level of voltage and a low voltage line which supplies a low level of voltage.Type: GrantFiled: December 29, 1995Date of Patent: November 11, 1997Assignee: NEC CorporationInventors: Tomofumi Iima, Masakazu Yamashina, Masayuki Mizuno
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Patent number: 5585754Abstract: An integrated digital circuit includes an oscillation circuit comprising basic gate circuits having the number of stages proportional to the number of gates existing in the critical path of a synchronized circuit network and capable of controlling an oscillating frequency by at least one control signal line. A synchronized circuit network constructed with basic gate circuits capable of controlling the delay time by at least one control signal line operates synchronously by an oscillation signal transfer line. A control circuit controls the oscillation circuit and the synchronized circuit network using the control signal line so that the frequency of signal input from an externally input signal line is equalized with the frequency of signal from the oscillation circuit.Type: GrantFiled: April 4, 1994Date of Patent: December 17, 1996Assignee: NEC CorporationInventors: Masakazu Yamashina, Masayuki Mizuno
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Patent number: 5559461Abstract: A drive circuit includes first and second circuit sections. The first circuit section maintains, during an initial stage of a transient period of an input signal, its output level before the signal transition and supplies after the transient period an output signal responsive to the signal transition. The second circuit section has a first circuit portion receiving the input signal and a second circuit portion, responsive to the input signal, and the output of the first circuit section, to accelerate the signal transition of the first circuit portion. Signal delay in a signal transition due to a large parasitic capacitance and resistance can be recovered by the drive circuit. The drive circuit has a large noise margin and operates at a high-speed and in a wide frequency range.Type: GrantFiled: June 27, 1995Date of Patent: September 24, 1996Assignee: NEC CorporationInventors: Masakazu Yamashina, Youichi Koseki, Masayuki Mizuno
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Patent number: 4985861Abstract: For improvement in processing speed, a high-speed digital signal processor has a feedback loop from a register which stores the calculating result produced by a Signed Digit (SD) arithmetic unit to one of the input ports of the SD arithmetic unit. The SD arithmetic unit executes an arithmetic operation on an input digital signal and the arithmetic result is formed of both signed digit numbers without the need to convert the calculation result represented by an SD number into a binary number.Type: GrantFiled: January 27, 1989Date of Patent: January 15, 1991Assignee: NEC CorporationInventors: Masakazu Yamashina, Hachiro Yamada, Tadayoshi Enomoto
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Patent number: 4849921Abstract: An arithmetic circuit has a first subtracter receiving first and second input signals which are composed of a plurality of bits and operative to output a first output signal representative of the first input signal minus the second input signal, and a second subtracter receiving the first and second input signals so as to output a second output signal representative of the second input signal minus the first input signal. A selector receives the first and second output signals and operates in response to one of the first and second output signals so as to alternately output the first and second output signals.Type: GrantFiled: June 19, 1986Date of Patent: July 18, 1989Assignee: NEC CorporationInventors: Masaaki Yasumoto, Tadayoshi Enomoto, Masakazu Yamashina