Abstract: The present disclosure provides, for example, a compound represented by the general formula below or a pharmaceutically acceptable salt thereof, or a pharmaceutically acceptable solvate of the compound or salt: wherein X1, X2, X3 and X4 are each independently —CR2? or N?, R2 is, for example, a halogen atom, R1 is, for example, —S(?O)2—NH—R8, R8 is, for example, a C1-6 alkyl group, R3 is, for example, a hydrogen atom, R5 is, for example, a halogen atom, R6 is, for example, a hydrogen atom, and R4 is, for example, a cyclopropyl group. The compounds, salts or solvates provided by the present disclosure exhibit high RAF/MEK complex-stabilizing activity and can be used for the treatment or prevention of cell proliferative disorders, particularly cancers.

Abstract: A tape affixing system capable of automatically switching or replacing a dicing tape. A tape affixing system 1 includes a stocker 5 that stores tape magazines 4 each accommodating a dicing tape DT wound in a roll shape, an affixing apparatus 3 which includes movable guide rollers 32a and 32b, fixed guide rollers 33a and 33b, and a knife plate 35 that regulate a reel-out region R of the dicing tape DT to a predetermined track, on which each of the tape magazines 4 is replaceably mountable, and which affixes the dicing tape DT to a dicing frame DT and a workpiece W, and a first conveyance robot 6 that delivers the tape magazine 4 between the stocker 5 and the affixing apparatus 3.

Abstract: A processing load is reduced when a flash memory is used. A storage management device acquires an archive associated with an application, stores the acquired archive to one or more blocks among a plurality of blocks contained in the flash memory, and deletes one block among the plurality of blocks. In the archive storage, the acquired archive is stored in one of the blocks not storing an archive associated with an application different from that of the acquired archive, and in the deletion of one block, when an application is deleted, a block storing an archive associated with the application to be deleted is deleted.

Abstract: A semiconductor memory device includes a memory cell, a reference cell, a first current source configured to cause a first current to flow through the memory cell, a second current source configured to cause a second current having an amount thereof being variable to flow through the reference cell, a sense amplifier configured to compare a voltage responsive to a voltage drop across the memory cell with a voltage responsive to a voltage drop across the reference cell, and a current-amount setting circuit configured to determine the amount of the second current, wherein the current-amount setting circuit determines the amount of the second current such that the voltage drop across the reference cell is equal to a midpoint between the voltage drop across the memory cell having a data value of “0” stored therein and the voltage drop across the memory cell having a data value of “1” stored therein.

Abstract: A semiconductor storage device includes: a memory cell array in which a plurality of pairs of bit lines and source lines, a plurality of word lines, and a plurality of resistance change memory cells are arranged; a write driver, a sense amplifier, a global bit line and a global source line provided on a first end side; a plurality of bit line switches provided between the plurality of bit lines and the global bit line; a plurality of source line switches provided between the plurality of source lines and the global source line; a column decoder; a row decoder; a plurality of bit line ground switches provided between the plurality of bit lines and a ground line on a second end side; and a plurality of source line ground switches provided between the plurality of source lines and a ground line on the second end side.

Abstract: A semiconductor memory device includes a memory cell, a reference cell, a first current source configured to cause a first current to flow through the memory cell, a second current source configured to cause a second current having an amount thereof being variable to flow through the reference cell, a sense amplifier configured to compare a voltage responsive to a voltage drop across the memory cell with a voltage responsive to a voltage drop across the reference cell, and a current-amount setting circuit configured to determine the amount of the second current, wherein the current-amount setting circuit determines the amount of the second current such that the voltage drop across the reference cell is equal to a midpoint between the voltage drop across the memory cell having a data value of “0” stored therein and the voltage drop across the memory cell having a data value of “1” stored therein.

Abstract: A semiconductor storage device includes: a memory cell array in which a plurality of pairs of bit lines and source lines, a plurality of word lines, and a plurality of resistance change memory cells are arranged; a write driver, a sense amplifier, a global bit line and a global source line provided on a first end side; a plurality of bit line switches provided between the plurality of bit lines and the global bit line; a plurality of source line switches provided between the plurality of source lines and the global source line; a column decoder; a row decoder; a plurality of bit line ground switches provided between the plurality of bit lines and a ground line on a second end side; and a plurality of source line ground switches provided between the plurality of source lines and a ground line on the second end side.

Abstract: A magnetic memory device including a multivalued magnetic memory cell whose electric resistances become first to fourth resistance value when first to fourth information are respectively stored, a first reference cell larger than the first resistance value and smaller than the second resistance value, a second reference cell larger than the second resistance value and smaller than the third resistance value, a third reference cell larger than the third resistance value and smaller than the fourth resistance value, and a read circuit including first to third comparators comparing a signal corresponding to the resistance of the magnetic memory cell and respective signals corresponding to the resistances of the first to third reference cells.

Abstract: A semiconductor memory includes a real memory cell including a selection transistor and a resistance variable element which are connected in series between a first voltage line and a second voltage line through a connection node, a real amplification transistor having a gate connected to the connection node, a source connected to a reference voltage line, and a drain connected to a real read line, and a sense amplifier to determine a logic held in the real memory cell by receiving a voltage of the real read line varied with a voltage generated in the connection node by resistance dividing between a source/drain resistance of the selection transistor, and the resistance variable element, the selection transistor receiving a read control voltage at the gate thereof.

Abstract: A method of writing into a semiconductor memory device, which includes a resistance memory element 14 which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage; a transistor 12 including a drain terminal connected to one terminal of the resistance memory element 14 and a source terminal connected to a reference voltage; and a transistor 16 including a source terminal connected to the other terminal of the resistance memory element 14.

Abstract: A semiconductor memory includes a real memory cell including a selection transistor and a resistance variable element which are connected in series between a first voltage line and a second voltage line through a connection node, a real amplification transistor having a gate connected to the connection node, a source connected to a reference voltage line, and a drain connected to a real read line, and a sense amplifier to determine a logic held in the real memory cell by receiving a voltage of the real read line varied with a voltage generated in the connection node by resistance dividing between a source/drain resistance of the selection transistor, and the resistance variable element, the selection transistor receiving a read control voltage at the gate thereof.

Abstract: A method of writing data into a memory cell of spin transfer torque magnetoresistive random access memory includes writing a first data into a first memory cell that includes a first magnetic-tunnel-junction element and a first selection transistor wherein an end of the first memory cell is connected to a first signal line and a different end of the first memory cell is connected to a common signal line during a first period, and writing a second data which is an opposite of the first data into the second memory cell that includes a second magnetic-tunnel-junction element and a second selection transistor wherein an end of the second memory cell is connected to a second signal line and a different end of the second memory cell is connected to the common signal line during a second period following the first period.

Abstract: A semiconductor storage device includes a semiconductor substrate, a source region, a source line, and a bit line. The source region is formed in an element region formed on the semiconductor substrate. The source line is formed to overlap with the source region in planar view. The bit line is formed on a layer higher than the source line.

Abstract: An ReRAM of the present invention includes a high speed write-in region and a main memory region, only memory cells designated to have the storage state out of the memory cells corresponded to data are set to the storage state in the high speed write-in region. The data written in the memory cell array are transferred to the main memory region, the memory cells of the memory cell array corresponded to the data transferred from the high speed write-in region are reset to the no-storage state in the main memory region, only the memory cells designated to have the storage state out of the memory cells are set, and all memory cells are reset to the no-storage state, or the initial state, in the high speed write-in region.

Abstract: In the semiconductor memory device having a resistance memory element, a first transistor having a drain terminal connected to one end of the resistance memory element and a source terminal connected to a ground voltage, and a second transistor having source terminal connected to the resistance memory element, when a write voltage is applied to the resistance memory element via the second transistor to switch the resistance memory element from a low resistance state to a high resistance state, a voltage is controlled to be a value which is not less than a reset voltage and less than a set voltage by applying to a gate terminal of the second transistor a voltage which is not less than a total of the reset voltage and a threshold voltage of the second transistor and is less than a total of the set voltage and the threshold voltage.

Abstract: The spin torque transfer magnetic random access memory includes a magnetic tunnel junction element including a pinned layer, a free layer, and a tunnel insulating film formed between the pinned layer and the free layer, and a memory cell select transistor having one diffused region electrically connected to a side of the fee layer of the magnetic tunnel junction element.

Abstract: An ReRAM of the present invention includes a high speed write-in region and a main memory region, only memory cells designated to have the storage state out of the memory cells corresponded to data are set to the storage state in the high speed write-in region. The data written in the memory cell array are transferred to the main memory region, the memory cells of the memory cell array corresponded to the data transferred from the high speed write-in region are reset to the no-storage state in the main memory region, only the memory cells designated to have the storage state out of the memory cells are set, and all memory cells are reset to the no-storage state, or the initial state, in the high speed write-in region.

Abstract: A magnetic memory device includes a memory cell including magnetoresistance effect elements MTJ1, MTJ2 and a select transistor connected to the connection node of the magnetoresistance effect elements MTJ1, MTJ2, a first signal line extended in a first direction and connected to the magnetoresistance effect element MTJ1, a second signal line extended in the first direction and connected to the magnetoresistance effect element MTJ2, and a third signal line extended in a second direction and crossing the first signal line in a region where the magnetoresistance effect element MTJ1 is formed and crossing the second signal line in a region where the magnetoresistance effect element MTJ2 is formed. When memory information is written into the memory cell, the memory information to be memorized is switched by directions of write currents to be flowed to the first and the second signal lines.

Abstract: A plasma display device has a first plate and a second plate which face each other with a discharge space therebetween, and a sealing member which is provided between the first and second plates to seal the discharge space at edges of the first and second plates. A plurality of electrodes are formed on the inner major surface of the first or second plate. An electrode diffusion preventive layer is formed in each area where the plurality of electrodes cross over the sealing member, so as to avoid direct contact between the plurality of electrodes and the sealing member. As a result, problems such as breaking of the electrodes can be avoided. This construction is especially effective when the electrodes contain Ag.

Abstract: The first object of the present invention is to provide a PDP with improved panel brightness which is achieved by improving the efficiency in conversion from discharge energy to visible rays. The second object of the present invention is to provide a PDP with improved panel life which is achieved by improving the protecting layer protecting the dielectrics glass layer. To achieve the first object, the present invention sets the amount of xenon in the discharge gas to the range of 10% by volume to less than 100% by volume, and sets the charging pressure for the discharge gas to the range of 500 to 760 Torr which is higher than conventional charging pressures. With such construction, the panel brightness increases. Also, to achieve the second object, the present invention has, on the surface of the dielectric glass layer, a protecting layer consisting of an alkaline earth oxide with (100)-face or (110)-face orientation.