Patents by Inventor Masaki Fujihara

Masaki Fujihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9417746
    Abstract: On a resin substrate (2) there are laminated, in the stated order, a conductive layer in which a bridge electrode (3b) and leads are formed, a first interlayer insulating layer (4), and an electrode layer that allows through visible light forming a unit electrode (5XU) of a drive electrode line (5X) and a unit electrode (5YU) of a sensing electrode line (5Y). It is accordingly possible to realize a touch panel substrate (1) capable of minimizing any increases in thickness, decreases in transmittance, complexity of terminal portions, and deterioration in optical characteristics.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: August 16, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kenshi Tada, Noriko Watanabe, Kenji Misono, Yasumori Fukushima, Masaki Fujihara, Shinsuke Saida
  • Publication number: 20140375910
    Abstract: On a resin substrate (2) there are laminated, in the stated order, a conductive layer in which a bridge electrode (3b) and leads are formed, a first interlayer insulating layer (4), and an electrode layer that allows through visible light forming a unit electrode (5XU) of a drive electrode line (5X) and a unit electrode (5YU) of a sensing electrode line (5Y). It is accordingly possible to realize a touch panel substrate (1) capable of minimizing any increases in thickness, decreases in transmittance, complexity of terminal portions, and deterioration in optical characteristics.
    Type: Application
    Filed: February 8, 2013
    Publication date: December 25, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kenshi Tada, Noriko Watanabe, Kenji Misono, Yasumori Fukushima, Masaki Fujihara, Shinsuke Saida
  • Patent number: 6271062
    Abstract: A thin film transistor includes: a substrate; a gate electrode, a source electrode and a drain electrode formed above the substrate; and an insulating film and a semiconductor film formed between the gate electrode, and the source electrode and the drain electrode, wherein the semiconductor film includes an i-type silicon film, and a portion of the semiconductor film within 50 nm from the insulating film has a microcrystalline structure having a conductivity of 5×10−10 S/cm or more.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: August 7, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yukihiko Nakata, Masaki Fujihara, Masahiro Date, Takuya Matsuo, Michiteru Ayukawa, Takashi Itoga
  • Patent number: 5796116
    Abstract: A thin film transistor includes: a substrate; a gate electrode, a source electrode and a drain electrode formed above the substrate; and an insulating film and a semiconductor film formed between the gate electrode, and the source electrode and the drain electrode, wherein the semiconductor film includes an i-type silicon film, and a portion or the semiconductor film within 50 nm from the insulating film has a microcrystalline structure having a conductivity of 5.times.10.sup.-10 S/cm or more.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: August 18, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yukihiko Nakata, Masaki Fujihara, Masahiro Date, Takuya Matsuo, Michiteru Ayukawa, Takashi Itoga
  • Patent number: 5771083
    Abstract: A liquid crystal display device incorporating an active matrix substrate having an inter-layer insulating film between a pixel electrode and gate and source signal lines. In this liquid crystal display device, the source signal line has a double-layer structure of an upper-layer line and a lower-layer line, but the upper-layer line is eliminated at the intersection of the gate signal line and the source signal line. This structure prevents a decrease in the thickness of the inter-layer insulating layer on the intersection of the gate signal line and the source signal line.
    Type: Grant
    Filed: October 1, 1996
    Date of Patent: June 23, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaki Fujihara, Yuzuru Kanemori, Masaya Okamoto