Patents by Inventor Masaki Ichihara

Masaki Ichihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020132581
    Abstract: The information terminal unit (3) comprises a transceiver (231) and a processor (232), while the variable directional antenna (1) comprises a main antenna element (201) to which the transceiver directly supplies a radio frequency signal, and a plurality of sub antenna elements (202 to 207). The sub antenna elements are connected with variable phase shifter circuits (212 to 217) for determining a phase shift amount of a reflecting wave, respectively. The control circuit (220) receives the directivity data from the CPU (232) of the information terminal unit (3) and analyzes the received data to control the phase shift amount of each variable phase shifter circuit (212 to 217) .
    Type: Application
    Filed: March 12, 2002
    Publication date: September 19, 2002
    Applicant: NEC CORPORATION
    Inventor: Masaki Ichihara
  • Patent number: 6434373
    Abstract: A transmission power control device is for use in a radio communication apparatus. The transmission power control device comprises a processing section for processing an input transmission signal into a processed transmission signal in accordance with a control signal. A power amplifier circuit has a first transistor for amplifying the processed transmission signal into a power amplified transmission signal. The transmission power control device further comprises a detecting circuit for detecting a current flowing through the first transistor to produce a current detection signal. A converting circuit converts the control signal into a reference value signal corresponding to a level of the processed transmission signal. A bias current section compares the current detection signal with the reference value signal to produce a comparison result signal. The bias current section controls a bias current for the amplifier circuit in accordance with the comparison result signal.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: August 13, 2002
    Assignee: NEC Corporation
    Inventor: Masaki Ichihara
  • Patent number: 6424124
    Abstract: A charging system for portable equipment is provided which may be used in a system including an information terminal and portable equipment connected to the information terminal. The charging system includes a power supply output device provided with the information terminal and a first battery control device provided with the portable equipment. The power supply output device is capable of supplying electric power, which is supplied to the information terminal, to the portable equipment. The first battery control device receives electric power supplied from the power supply output device and performs a charging operation for a battery of the portable equipment.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: July 23, 2002
    Assignee: NEC Corporation
    Inventors: Masaki Ichihara, Kozo Maemura
  • Publication number: 20020089384
    Abstract: A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO) having a parallel resonant circuit including a first capacitance implemented by a reverse-biased diode and a second capacitance implemented by MOS capacitors. Upon lock-in of the oscillation frequency with respect to the reference frequency, whether the oscillation frequency has a deviation is examined based on the tune voltage controlling the first variable capacitance. If a deviation is observed due to a temperature fluctuation etc., the control voltage for the second variable capacitance is corrected for compensating the deviation.
    Type: Application
    Filed: December 21, 2001
    Publication date: July 11, 2002
    Applicant: NEC CORPORATION
    Inventor: Masaki Ichihara
  • Publication number: 20020047744
    Abstract: An object of the present invention is to suppress the generation of a transient voltage in the settings of gains of a plurality of variable gain amplifiers of a baseband circuit. A gain converting circuit provides a limiting value to the quantity of the change of a gain which can be changed once. If gain input data has large change and the gain change exceeding the limiting value is carried out, the quantity of the change is divided into a plurality of quantities of change equal to or lower than the limiting value and variable gain amplifiers are controlled to thereby realize a required gain change. A gain distribution circuit distributes gain control data to the respective variable gain amplifiers on the basis of gain output data of the gain converting circuit.
    Type: Application
    Filed: September 13, 2001
    Publication date: April 25, 2002
    Applicant: NEC Corporation
    Inventor: Masaki Ichihara
  • Patent number: 6373880
    Abstract: In scramble calculation by a complex multiplier used for a frequency spread modulation circuit of this invention, the scramble circuit can be simplified because input signals are processed as binary numbers. Other arithmetic processing operations are implemented by simple data selectors. The circuit scale can be reduced, and the process delay time can be considerably shortened.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventor: Masaki Ichihara
  • Publication number: 20020037706
    Abstract: A base band circuit forms a part of an automatic gain controller incorporated in a direct conversion receiver, and includes a series of variable gain amplifiers controlled by a gain controller and a feedback loop connected between the output node and the input node of the series of variable gain amplifiers, wherein the feedback loop has an attenuation circuit connected between the output node of the series of variable gain amplifiers and an inverted integrating circuit which, in turn, is connected through an adder and a low pass filter to the input node of the series of variable gain amplifiers so that direct current offset voltage is eliminated from the output signal of the series of variable gain amplifiers without change of cut-off frequency.
    Type: Application
    Filed: September 26, 2001
    Publication date: March 28, 2002
    Applicant: NEC Corporation
    Inventor: Masaki Ichihara
  • Publication number: 20010053124
    Abstract: To provide an orthogonal frequency division multiplex modem circuit which can multiplex signals, whose bit rates and QoS are different from one another, and can transmit the signals via one OFDM line. A serial/parallel converter converts input signals into a complex parallel signal respectively, and a sub carrier and a modulation system are assigned every communication channel. A randomizer changes the alignment sequence of the signal, a discrete inverse Fourier transformer processes the signal, a parallel/serial converter converts the signal into a serial signal, and a transmitter performs the orthogonal modulation of the signal to output the signal from an antenna. A receiver performs orthogonal demodulation of the signal received with an antenna, a serial/parallel converter converts the signal into a parallel signal, and a discrete Fourier transformer processes the parallel signal.
    Type: Application
    Filed: June 12, 2001
    Publication date: December 20, 2001
    Applicant: NEC Corporation
    Inventors: Masaki Ichihara, Yukitsuna Furuya
  • Publication number: 20010051507
    Abstract: A receiver of the direct conversion system by which problems arising from interference between a reception signal and a local signal used by a quadrature demodulator on the reception side are moderated. Where the carrier frequency of a transmission signal is represented by ft and the carrier frequency of a reception signal by fr while the frequency interval between the transmission and reception carrier frequencies is represented by fs (=fr −ft), first and second local oscillators generate first and second local signals fLO1, fLO2 having frequencies fLO1 ≈ft −fs and fLO2 ≈2·fs, respectively. A mixer mixes the first and second local signals to generate an internal local signal which is a sum frequency component. The internal local signal is supplied to a quadrature demodulator of the reception side. The mixer and a band-pass filter are formed in the same LSI chip as the quadrature demodulator.
    Type: Application
    Filed: June 8, 2001
    Publication date: December 13, 2001
    Applicant: NEC Corporation
    Inventor: Masaki Ichihara
  • Patent number: 6330455
    Abstract: Disclosed is a transmission power controller to prevent a transmission power from being excessive in mobile communication terminal equipment that requires a precise transmission power control. Branching filter 11, detector 12 and smoothing circuit 13 in combination generate a detected voltage corresponding to an average transmission power from the mobile communication terminal equipment. Threshold setting circuit 14 generates a threshold voltage corresponding to an allowable maximum average transmission power. Voltage comparator 15 decides if the average transmission power from the mobile communication terminal equipment is higher or lower than the allowable maximum average transmission power by comparing the detected voltage with the threshold voltage. Controller 16 varies a control voltage so as to lower a gain of a variable gain amplifier 4 if the average transmission power is decided to be higher than the allowable maximum average transmission power.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: December 11, 2001
    Assignee: NEC Corporation
    Inventor: Masaki Ichihara
  • Publication number: 20010029466
    Abstract: A rewarding method corresponding to an object selection on a web page, comprising the steps of: (a) designating a predetermined object to each of a plurality of web pages having respective URLs; (b) causing a server to detect that a user of a user terminal unit has selected the object on one of the plurality of web pages having respective URLs; (c) recording an event log correlating an identifier of the user, an identifier of the selected object, and an event that the object has been selected, when the server detects that the user of the user terminal unit has selected the object; (d) determining whether or not the number of objects recorded in the event log exceeds a first predetermined value; and (e) performing a rewarding process to reward the user when the determined result at the step (d) is Yes.
    Type: Application
    Filed: April 2, 2001
    Publication date: October 11, 2001
    Applicant: NEC COPORATION
    Inventor: Masaki Ichihara
  • Publication number: 20010022821
    Abstract: A novel amplitude deviation correction circuit which corrects an amplitude deviation between an I signal and a Q signal is disclosed. An average amplitude deviation between an I signal amplified by a variable gain amplifier and a Q signal amplified by another variable gain amplifier is detected by an amplitude comparison circuit, and +1 volt or −1 volt is outputted in response to a result of the detection. An integration circuit integrates the output of the amplitude comparison circuit and controls the gains of the variable gain amplifiers in response to a result of the integration.
    Type: Application
    Filed: March 2, 2001
    Publication date: September 20, 2001
    Inventor: Masaki Ichihara
  • Publication number: 20010014587
    Abstract: A transmission power control device is for use in a radio communication apparatus. The transmission power control device comprises a processing section for processing an input transmission signal into a processed transmission signal in accordance with a control signal. A power amplifier circuit has a first transistor for amplifying the processed transmission signal into a power amplified transmission signal. The transmission power control device further comprises a detecting circuit for detecting a current flowing through the first transistor to produce a current detection signal. A converting circuit converts the control signal into a reference value signal corresponding to a level of the processed transmission signal. A bias current section compares the current detection signal with the reference value signal to produce a comparison result signal. The bias current section controls a bias current for the amplifier circuit in accordance with the comparison result signal.
    Type: Application
    Filed: August 3, 1998
    Publication date: August 16, 2001
    Inventor: MASAKI ICHIHARA
  • Patent number: 6275699
    Abstract: In a mobile communication terminal, a switch 10 is initially set to an initial setting mode at time of turning on a power supply. A reference oscillator control circuit is initialized, and in this state, the output frequency of a reference oscillator is usually greatly shifted. The base station search is first conducted, and as a result, if the base station cannot be grasped, an offset signal is generated by a frequency offset generating circuit 12, to shift the output frequency of a reference oscillator 6 through a reference oscillator control circuit 5. This operation is repeated until the base station is grasped so that the base station search is continued while the output frequency of the reference oscillator 6 is being shifted. When a grasp of the base station succeeds, the switch 10 is switched to an AFC side to conduct automatic frequency adjustment.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: August 14, 2001
    Assignee: NEC Corporation
    Inventor: Masaki Ichihara
  • Patent number: 6275558
    Abstract: A circuit, which shifts an M-sequence code with an arbitrary number of bits, is realized by a small circuit scale. D-type flip-flops 1-6 form a shift register for generating an M-sequence and having outputs d0-d5 of respective stages, to which 25 bit shift inserting circuit 10 is connected in the manner of receiving the outputs d0-d5 as respective inputs and of outputting outputs O0-O5, to which 24 bit shift inserting circuit 11 is connected in the manner of receiving the outputs O0-O5 as respective inputs. In the same manner, a 23 bit shift inserting circuit 12, a 22 bit shift inserting circuit 13, a 21 bit shift inserting circuit 14, and a 20 bit shift inserting circuit 15 are sequentially connected with one another. Each of bit shift inserting circuits 10-15 respectively shifts a predetermined bit when control signals b5-b0 are “1”, and does not shift a bit when “0” so as to output an input as it is. Therefore, it is possible to obtain an arbitrary bit shift.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: August 14, 2001
    Assignee: NEC Corporation
    Inventor: Masaki Ichihara
  • Publication number: 20010005126
    Abstract: A charging system for portable equipment is provided which may be used in a system including an information terminal and portable equipment connected to the information terminal. The charging system includes a power supply output device provided with the information terminal and a first battery control device provided with the portable equipment. The power supply output device is capable of supplying electric power, which is supplied to the information terminal, to the portable equipment. The first battery control device receives electric power supplied from the power supply output device and performs a charging operation for a battery of the portable equipment.
    Type: Application
    Filed: December 27, 2000
    Publication date: June 28, 2001
    Inventors: Masaki Ichihara, Kozo Maemura
  • Patent number: 6249560
    Abstract: The frequency divider output a2 is provided to the D input of a first D flip-flop and an input clock a1 to a first frequency divider is inversed by an inverter and is then provided to the C input of the first D flip-flop. The first frequency divider output b2 is provided to the D input of a second D flip-flop, and an input clock b1 to a second frequency divider is inversed by another inverter and then sent to the input C of the second D flip-flop. The Q output of the first D flip-flop and the Q output of the second D flip-flop are sent to a phase comparator as the output signal a3 and the output signal b3, respectively. In this way, the frequency divider outputs a2 and b2 are taken into the first and second D flip-flops at a point half behind the input clocks a1 and b2 and are provided to the phase comparator as the output signals a3 and b3.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: June 19, 2001
    Assignee: NEC Corporation
    Inventor: Masaki Ichihara
  • Patent number: 6229840
    Abstract: Radio-frequency signals received by two antennas are respectively amplified by two amplifiers. Of the two signals, only the radio-frequency signal received by the second antenna is delayed by a delay time T through a delay circuit. The output from the delay circuit and the output from the first amplifier connected to the first antenna are combined by a combiner. From this stage toward subsequent stages, a shared receiver lowers the frequency of the combined signal to that of a base band signal, which is converted into a digital signal by a shared A/D converter. This digital signal is demodulated by a Rake receiver, and the demodulated result is decoded by the decoder to reproduce transmitted data.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: May 8, 2001
    Assignee: NEC Corporation
    Inventor: Masaki Ichihara
  • Patent number: 6097713
    Abstract: In a CDMA multi-code transmitter in which data signals input from a plurality of data channels are spectrum-spread with mutually different spreading codes and resultant baseband signals are summed and transmitted, peak values of an eye-pattern is reduced to reduce power consumption by delaying the baseband signals before summed, such that transmission timings of the respective baseband signals are mutually shifted.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: August 1, 2000
    Assignee: NEC Corporation
    Inventor: Masaki Ichihara
  • Patent number: 6097715
    Abstract: In a CDMA communication system, a base station includes a spreader 11 for spreading a frequency of a standby control signal by using a short code, a differential coder 12 for differential-coding the spread standby control signal and adders 13a and 13b for adding the differential-coded signal to an I channel signal and a Q channel signal, respectively, and a terminal station includes a differencial detector 14 for differencial-detecting a receiving signal and a matched filter 15 for inverse-spreading a differencial-detected baseband signal, wherein a complete intermittent operation of the terminal station in a standby state is realized and a power consumption of the terminal station is reduced by transmitting the standby control signal containing an information indicative of the terminal station and an intermittent interval from the base station to the terminal station.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: August 1, 2000
    Assignee: NEC Corporation
    Inventor: Masaki Ichihara