Patents by Inventor Masaki Naganawa

Masaki Naganawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8373453
    Abstract: A circuit including a first buffer coupled to a power line to output a first output signal based on a data signal to an output terminal, a second buffer coupled to the power line to output a second output signal based on the data signal to the output terminal when a control signal is in a predetermined level, and a control circuit coupled to the power line and the control signal.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Masaki Naganawa
  • Publication number: 20120262134
    Abstract: A circuit including a first buffer coupled to a power line to output a first output signal based on a data signal to an output terminal, a second buffer coupled to the power line to output a second output signal based on the data signal to the output terminal when a control signal is in a predetermined level, and a control circuit coupled to the power line and the control signal.
    Type: Application
    Filed: April 18, 2012
    Publication date: October 18, 2012
    Applicant: Renesas Electronics Corporation
    Inventor: Masaki Naganawa
  • Patent number: 8183891
    Abstract: A semiconductor device includes an interface circuit that varies drive ability according to a control signal, and a control circuit that generates the control signal according to a range of an output voltage of the interface circuit. The interface circuit and the control circuit are provided on one chip.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: May 22, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Masaki Naganawa
  • Publication number: 20090237145
    Abstract: A semiconductor device includes an interface circuit that varies drive ability according to a control signal, and a control circuit that generates the control signal according to a range of an output voltage of the interface circuit. The interface circuit and the control circuit are provided on one chip.
    Type: Application
    Filed: February 26, 2009
    Publication date: September 24, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Masaki Naganawa