Patents by Inventor Masaki Nakanishi

Masaki Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080253100
    Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 16, 2008
    Inventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
  • Publication number: 20080248611
    Abstract: The quality and reliability of a semiconductor device can be improved by eliminating a warp of a chip and performing a chip-stack. A wiring substrate, the first semiconductor chip connected via the first gold bump on the wiring substrate, the second semiconductor chip stacked via the second gold bump on the first semiconductor chip, and a sealing body are comprised. A first gold bump is connected to the wiring substrate, heating, and injection by pressure welding of the first gold bump is done under normal temperature after that at the hole-like electrode of the first semiconductor chip. Since injection by pressure welding of the second gold bump of the second semiconductor chip is done under normal temperature into the hole-like electrode of the first semiconductor chip and the second semiconductor chip is stacked, the chip-stack can be performed under normal temperature.
    Type: Application
    Filed: February 27, 2008
    Publication date: October 9, 2008
    Inventors: Kenji HANADA, Norihisa Toma, Masaki Nakanishi, Takahiro Naito, Naotaka Tanaka
  • Patent number: 7396701
    Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
  • Publication number: 20060161773
    Abstract: A node 10 is provided with an internal memory 42 for saving a program transmitted from a server 20, a CPU 41 for executing the program saved in the internal memory 42, a hash value calculating section 103 for performing an operation of the program executed by the CPU 41 using a specified hash function when the execution of the program is completed, and a digital signature executing section 104 for digitally signing the program operated using the hash function and the execution result of the program, using a secret key peculiar to the node 10 and saved in a secret key storage 105. Accordingly, there can be provided a microprocessor capable of guaranteeing that the content of a memory is not unjustly falsified during the execution of the program, a node terminal provided with such a microprocessor and capable of proving the execution of the program, a computer system and a program execution proving method.
    Type: Application
    Filed: July 13, 2005
    Publication date: July 20, 2006
    Inventors: Atsuya Okazaki, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe
  • Publication number: 20060110859
    Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.
    Type: Application
    Filed: November 18, 2005
    Publication date: May 25, 2006
    Inventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
  • Publication number: 20060091487
    Abstract: A sensor chip and a lens mount accommodating therein the sensor chip are mounted on a surface of a wiring substrate and a lens holder accommodating a lens therein is coupled with the lens mount. On a rear surface of the wiring substrate, a logic chip, a memory chip and a passive component are mounted and they are sealed with a seal resin. An electrode pad of the sensor chip is electrically connected to an electrode on the surface of the wiring substrate via a bonding wire but a stud bump is also formed on the electrode at the surface of the wiring substrate and this stud bump is connected with the bonding wire. On the surface of the wiring substrate, a flexible substrate is bonded with an anisotropic conductive film and a bonding material. When a camera module is to be manufactured, the surface side of the wiring substrate is assembled after the rear surface side of the wiring substrate is assembled.
    Type: Application
    Filed: December 16, 2005
    Publication date: May 4, 2006
    Inventors: Kenji Hanada, Masaki Nakanishi, Tomoo Matsuzawa, Koji Shida, Kazutoshi Takashima
  • Patent number: 7005310
    Abstract: A sensor chip and a lens mount accommodating therein the sensor chip are mounted on a surface of a wiring substrate and a lens holder accommodating a lens therein is coupled with the lens mount. On a rear surface of the wiring substrate, a logic chip, a memory chip and a passive component are mounted and they are sealed with a seal resin. An electrode pad of the sensor chip is electrically connected to an electrode on the surface of the wiring substrate via a bonding wire but a stud bump is also formed on the electrode at the surface of the wiring substrate and this stud bump is connected with the bonding wire. On the surface of the wiring substrate, a flexible substrate is bonded with an anisotropic conductive film and a bonding material. When a camera module is to be manufactured, the surface side of the wiring substrate is assembled after the rear surface side of the wiring substrate is assembled.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: February 28, 2006
    Assignees: Renesas Technology Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Kenji Hanada, Masaki Nakanishi, Tomoo Matsuzawa, Koji Shida, Kazutoshi Takashima
  • Publication number: 20050116138
    Abstract: The reliability and production yield of a solid state image sensing device is improved. Over a surface of a wiring substrate, a sensor chip and a lens-barrel having the sensor chip housed therein are mounted. To the lens-barrel, a lens holder for retaining a lens is connected. Over a back surface of the wiring substrate, a logic chip, a memory chip and a passive part are mounted, and they are sealed with a sealing resin. The lens-barrel and lens holder are each threaded. They are thermally welded while the threads are fitted to each other. The passive part is bonded to the wiring substrate via a Sn—Ag type Pb-free solder. After the wiring substrate is subjected to plasma washing treatment, the sensor chip is mounted over the wiring substrate and an electrode pad of the sensor chip and an electrode of the wiring substrate are electrically connected via a bonding wire.
    Type: Application
    Filed: September 22, 2004
    Publication date: June 2, 2005
    Inventors: Kenji Hanada, Masaki Nakanishi, Kunio Shigemura, Takaomi Nishi, Koji Shida, Izumi Tezuka, Shunichi Abe, Yoshihiro Tomita, Mitsuaki Seino, Tohru Komatsu
  • Publication number: 20040166763
    Abstract: A sensor chip and a lens mount accommodating therein the sensor chip are mounted on a surface of a wiring substrate and a lens holder accommodating a lens therein is coupled with the lens mount. On a rear surface of the wiring substrate, a logic chip, a memory chip and a passive component are mounted and they are sealed with a seal resin. An electrode pad of the sensor chip is electrically connected to an electrode on the surface of the wiring substrate via a bonding wire but a stud bump is also formed on the electrode at the surface of the wiring substrate and this stud bump is connected with the bonding wire. On the surface of the wiring substrate, a flexible substrate is bonded with an anisotropic conductive film and a bonding material. When a camera module is to be manufactured, the surface side of the wiring substrate is assembled after the rear surface side of the wiring substrate is assembled.
    Type: Application
    Filed: August 29, 2003
    Publication date: August 26, 2004
    Inventors: Kenji Hanada, Masaki Nakanishi, Tomoo Matsuzawa, Koji Shida, Kazutoshi Takashima
  • Patent number: 6492195
    Abstract: Disclosed herein is a technique which performs the thinning of a wafer and the separation thereof from a support substrate with high yields and in a short time. Described specifically, a hole-free support substrate is bonded to a second surface of a support substrate having holes with an adhesive layer melted by heating so as to bloc the holes. A wafer is bonded to a first surface of the support substrate having the holes with an adhesive layer melted by solvent. The wafer is thinned by grinding and etching. The adhesive layer is melted by heating and the support substrate having the holes is slid with respect to the hole-free support substrate to thereby separate the support substrate having the holes from the hole-free support substrate. Further, the adhesive layer is melted by solvent from the holes defined in the support substrate having the holes to thereby separate the wafer from the support substrate having the holes.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: December 10, 2002
    Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Masaki Nakanishi, Susumu Sorimachi, Kiichi Yamashita, Hiroji Yamada, Kikuo Fukushima
  • Publication number: 20010005043
    Abstract: Disclosed herein is a technique which performs the thinning of a wafer and the separation thereof from a support substrate with high yields and in a short time. Described specifically, a hole-free support substrate is bonded to a second surface of a support substrate having holes with an adhesive layer melted by heating so as to bloc the holes. A wafer is bonded to a first surface of the support substrate having the holes with an adhesive layer melted by solvent. The wafer is thinned by grinding and etching. The adhesive layer is melted by heating and the support substrate having the holes is slid with respect to the hole-free support substrate to thereby separate the support substrate having the holes from the hole-free support substrate. Further, the adhesive layer is melted by solvent from the holes defined in the support substrate having the holes to thereby separate the wafer from the support substrate having the holes.
    Type: Application
    Filed: December 13, 2000
    Publication date: June 28, 2001
    Inventors: Masaki Nakanishi, Susumu Sorimachi, Kiichi Yamashita, Hiroji Yamada, Kikuo Fukushima