Abstract: To simplify the interconnection of signal lines in an imaging element including two semiconductor chips. An imaging element includes a pixel chip and a circuit chip. The pixel chip includes a plurality of pixels each including a charge transfer section configured to transfer a charge generated in accordance with incident light to a charge retention section in accordance with a control signal, and a plurality of first control signal transmission sections each configured to transmit the control signal for each of the charge transfer sections. The circuit chip includes a control signal generation section configured to generate the control signal for each of the charge transfer sections of the plurality of pixels, and a plurality of second control signal transmission sections provided to individually correspond to the first control signal transmission sections and each configured to transmit the generated control signal.

Abstract: To simplify the interconnection of signal lines in an imaging element including two semiconductor chips. An imaging element includes a pixel chip and a circuit chip. The pixel chip includes a plurality of pixels each including a charge transfer section configured to transfer a charge generated in accordance with incident light to a charge retention section in accordance with a control signal, and a plurality of first control signal transmission sections each configured to transmit the control signal for each of the charge transfer sections. The circuit chip includes a control signal generation section configured to generate the control signal for each of the charge transfer sections of the plurality of pixels, and a plurality of second control signal transmission sections provided to individually correspond to the first control signal transmission sections and each configured to transmit the generated control signal.

Abstract: Disclosed is a solid-state imaging device including a pixel array, a pixel signal generation part, and a control part. The pixel signal generation part includes a comparator and a counter. In a case where an enable signal is supplied from the control part, a count value of the counter in a D-phase period where a signal level is detected is set as a limit value regardless of an output of the comparator when a count value of the counter in a P-phase period where a reset level is detected is a limit value.

Abstract: Disclosed is a solid-state imaging device including a pixel array, a pixel signal generation part, and a control part. The pixel signal generation part includes a comparator and a counter. In a case where an enable signal is supplied from the control part, a count value of the counter in a D-phase period where a signal level is detected is set as a limit value regardless of an output of the comparator when a count value of the counter in a P-phase period where a reset level is detected is a limit value.