Patents by Inventor Masaki OYA

Masaki OYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395750
    Abstract: A first intermediate layer is a semiconductor layer provided on a first active layer, and is positioned between the first active layer and a second active layer. The first intermediate layer is structured so that a non-doped layer and an n-type layer are laminated in the order from the first active layer side. A second intermediate layer is a semiconductor layer provided on the second active layer, and is positioned between the second active layer and the third active layer. The second intermediate layer is structured so that a non-doped layer and an n-type layer are laminated in the order from the second active layer side.
    Type: Application
    Filed: May 25, 2023
    Publication date: December 7, 2023
    Inventors: Koji OKUNO, Koichi GOSHONOO, Masaki OYA
  • Publication number: 20230393205
    Abstract: Provided are a computer program, a determination device, and a determination method. A computer is caused to execute a process of estimating a state of at least one of an energy storage device and a charge system by executing a simulation using a battery model for simulating the energy storage device and a charge system model for simulating the charge system that charges the energy storage device and determining the compatibility between the energy storage device and the charge system based on the estimated state.
    Type: Application
    Filed: September 22, 2021
    Publication date: December 7, 2023
    Inventors: Masaki OYA, Yu MATSUMOTO, Shinichi NAMITOKO, Seiji TAKAI, Eiji HAYASHI
  • Publication number: 20230382231
    Abstract: A computer is caused to execute a process of; executing, for a system including an energy storage device and a powered unit driven by power supplied from the energy storage device wherein the energy storage device including a switch for switching between energized and non-energized states and having a switch self-diagnosis function, a simulation regarding switch self-diagnosis using a battery model for simulating the energy storage device and a powered-unit model for simulating the powered unit; and determining compatibility between the energy storage device and the powered unit based on an execution result of the simulation.
    Type: Application
    Filed: August 25, 2021
    Publication date: November 30, 2023
    Inventors: Yu MATSUMOTO, Seiji TAKAI, Eiji HAYASHI, Shinichi NAMITOKO, Masaki OYA
  • Patent number: 11462659
    Abstract: Provided is a semiconductor light emitting device including a growth substrate; a pillar-shaped semiconductor layer formed on the growth substrate; and a buried semiconductor layer formed to cover the pillar-shaped semiconductor layer, wherein the pillar-shaped semiconductor layer has an n-type nanowire layer formed at a center, an active layer formed on an outermore side than the n-type nanowire layer, a p-type semiconductor layer formed on an outermore side than the active layer and a tunnel junction layer formed on an outermore side than the p-type semiconductor layer, and wherein at least a part of the pillar-shaped semiconductor layer is provided with a removed region formed by removing from the buried semiconductor layer to a part of the tunnel junction layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: October 4, 2022
    Assignees: KOITO MANUFACTURING CO., LTD., MEIJO UNIVERSITY, TOYODA GOSEI CO., LTD.
    Inventors: Satoshi Kamiyama, Tetsuya Takeuchi, Motoaki Iwaya, Isamu Akasaki, Lu Weifang, Naoki Sone, Kazuyoshi Iida, Ryo Nakamura, Masaki Oya
  • Publication number: 20220285580
    Abstract: The semiconductor light-emitting device includes an n-type semiconductor layer, a plurality of columnar semiconductors on the n-type semiconductor layer, a buried layer filling in a space between the columnar semiconductors, and a current suppression region suppressing a current. The columnar semiconductors has a hexagonal column and an active layer covering the hexagonal column. The hexagonal column has a hexagonal first surface and a second surface opposite to the first surface. The first surface of the columnar semiconductors faces the base layer. The second surface of the columnar semiconductors faces the current suppression region.
    Type: Application
    Filed: February 16, 2022
    Publication date: September 8, 2022
    Inventors: Koji Okuno, Koichi MUZUTANI, Masaki OYA, Kazuyoshi IIDA, Satoshi KAMIYAMA, Tetsuya TEKEUCHI, Motoaki IWAYA, Isamu AKASAKI
  • Publication number: 20220246793
    Abstract: To suppress current leakage between the semiconductor layer below the mask and the buried layer above the mask. To reduce the drive voltage and improve the emission efficiency by improving the efficiency of carrier injection into the active layer. The semiconductor light-emitting device includes a substrate, a mask, a columnar semiconductor, a buried layer, a cathode electrode, and an anode electrode. The substrate has a conductive substrate, an n-type semiconductor layer disposed on the conductive substrate, and a p-type semiconductor layer disposed on the n-type semiconductor layer. The p-type semiconductor layer has a high resistance, thereby enhancing insulation between the n-type semiconductor layer and the buried layer.
    Type: Application
    Filed: January 21, 2022
    Publication date: August 4, 2022
    Inventors: Koji OKUNO, Koichi MIZUTANI, Masaki OYA, Kazuyoshi IIDA, Satoshi KAMIYAMA, Tetsuya TAKEUCHI, Motoaki IWAYA, Isamu AKASAKI
  • Publication number: 20220246789
    Abstract: A buried layer forming step includes three steps of a facet structure forming step, a c-plane forming step, and a flattening step. In the facet structure forming step, a buried layer grows to form a periodic facet structure that matches an arrangement pattern of columnar semiconductors. In the c-plane forming step, the buried layer grows such that a {0001} plane (upper surface) is formed in a region of the buried layer corresponding to an upper portion of the columnar semiconductor. In the flattening step, lateral growth of the buried layer is promoted and the c-plane formed in the c-plane forming step is widened to flatten a surface of the buried layer.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 4, 2022
    Inventors: Koji OKUNO, Koichi MIZUTANI, Masaki OYA, Kazuyoshi IIDA, Naoki SONE, Satoshi KAMIYAMA, Tetsuya TAKEUCHI, Motoaki IWAYA, Isamu AKASAKI
  • Publication number: 20210074877
    Abstract: Provided is a semiconductor light emitting device including a growth substrate; a pillar-shaped semiconductor layer formed on the growth substrate; and a buried semiconductor layer formed to cover the pillar-shaped semiconductor layer, wherein the pillar-shaped semiconductor layer has an n-type nanowire layer formed at a center, an active layer formed on an outermore side than the n-type nanowire layer, a p-type semiconductor layer formed on an outermore side than the active layer and a tunnel junction layer formed on an outermore side than the p-type semiconductor layer, and wherein at least a part of the pillar-shaped semiconductor layer is provided with a removed region formed by removing from the buried semiconductor layer to a part of the tunnel junction layer.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 11, 2021
    Applicants: KOITO MANUFACTURING CO., LTD., MEIJO UNIVERSITY, TOYODA GOSEI CO., LTD.
    Inventors: Satoshi Kamiyama, Tetsuya Takeuchi, Motoaki Iwaya, Isamu Akasaki, Lu Weifang, Naoki Sone, Kazuyoshi Iida, Ryo Nakamura, Masaki Oya
  • Patent number: 10825971
    Abstract: A light-emitting device includes a light-emitting element mounted on a base substrate, a reflective member that is formed on the base substrate and surrounds the light-emitting element, a transparent member that has a flat upper surface and is placed to cover above the light-emitting element, and a DBR film placed on the upper surface of the transparent member. A relation between an incident angle of light emitted from the light-emitting element and input into the DBR film and a transmittance of the light to pass through the DBR film is obtained such that a peak of the transmittance is in a range of the incident angle greater than 0°.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: November 3, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Masaki Oya, Takashi Mizobuchi
  • Publication number: 20190165227
    Abstract: A light-emitting device includes a light-emitting element mounted on a base substrate, a reflective member that is formed on the base substrate and surrounds the light-emitting element, a transparent member that has a flat upper surface and is placed to cover above the light-emitting element, and a DBR film placed on the upper surface of the transparent member. A relation between an incident angle of light emitted from the light-emitting element and input into the DBR film and a transmittance of the light to pass through the DBR film is obtained such that a peak of the transmittance is in a range of the incident angle greater than 0°.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 30, 2019
    Inventors: Masaki OYA, Takashi MIZOBUCHI