Patents by Inventor Masaki Uehata

Masaki Uehata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967294
    Abstract: A common electrode driver includes an inverting amplifier including a first resistor, a second resistor, and an operational amplifier, and a resistance ratio adjustment circuit that adjusts, in accordance with a length of one horizontal scan period, a resistance ratio being a ratio of a resistance value of the second resistor to a resistance value of the first resistor. A feedback voltage is provided to one end of the first resistor. The resistance ratio adjustment circuit sets the resistance ratio when second driving is performed, in which a length of one horizontal scan period is a second time longer than a first time, to be smaller than the resistance ratio when first driving is performed, in which a length of one horizontal scan period is the first time.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: April 23, 2024
    Assignee: Sharp Display Technology Corporation
    Inventors: Masaki Uehata, Yasuki Mori, Kohji Saitoh, Takayuki Mizunaga, Kazuya Kondoh, Takashi Nojima, Kazuhisa Yoshimoto, Kosuke Kawamoto, Hiroyuki Kito, Kazuki Nakamichi
  • Publication number: 20240005885
    Abstract: A common electrode driver includes an inverting amplifier including a first resistor, a second resistor, and an operational amplifier, and a resistance ratio adjustment circuit that adjusts, in accordance with a length of one horizontal scan period, a resistance ratio being a ratio of a resistance value of the second resistor to a resistance value of the first resistor. A feedback voltage is provided to one end of the first resistor. The resistance ratio adjustment circuit sets the resistance ratio when second driving is performed, in which a length of one horizontal scan period is a second time longer than a first time, to be smaller than the resistance ratio when first driving is performed, in which a length of one horizontal scan period is the first time.
    Type: Application
    Filed: May 1, 2023
    Publication date: January 4, 2024
    Applicant: Sharp Display Technology Corporation
    Inventors: Masaki UEHATA, Yasuki MORI, Kohji SAITOH, Takayuki MIZUNAGA, Kazuya KONDOH, Takashi NOJIMA, Kazuhisa YOSHIMOTO, Kosuke KAWAMOTO, Hiroyuki KITO, Kazuki NAKAMICHI
  • Patent number: 10896650
    Abstract: A short-circuiting circuit short-circuits source bus lines such that a sum of numbers assigned to two source bus lines forming each set in each group is equal for all sets when it is assumed that K consecutive source bus lines (K is an even number greater than or equal to 4) form one group and numbers from 1 to K are assigned to the K source bus lines. For example, with four consecutive source bus lines forming one group, in each group, the short-circuiting circuit short-circuits the first and fourth source bus lines and short-circuits the second and third source bus lines.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: January 19, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kohji Saitoh, Kosuke Kawamoto, Kazuhisa Yoshimoto, Kazuya Kondoh, Masaki Uehata, Yasuki Mori
  • Patent number: 10810959
    Abstract: A display device includes a display panel having a display surface, display drivers arranged on and along a peripheral portion of the display panel, a wiring substrate located on a side of the display panel opposite from the display surface and having a long shape extending in an arrangement direction of the display drivers, first flexible wiring substrates electrically connecting the display drivers to the wiring substrate, a second flexible wiring substrate extending from the wiring substrate toward an outer periphery of the display panel, and a control board connected to an extended end portion of the second flexible wiring substrate and configured to control the display drivers and disposed not to overlap the display panel in a thickness direction of the display panel and having a dimension in the thickness direction of the display panel larger than that of the wiring substrate.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 20, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhisa Yoshimoto, Kohji Saitoh, Yasuki Mori, Masaki Uehata, Kazuya Kondoh, Kosuke Kawamoto
  • Publication number: 20200286437
    Abstract: A display device includes a display panel having a display surface display rivers arranged on and along a peripheral portion of the display panel, a wiring substrate located on a side of the display panel opposite from the display surface and having a long shape extending in an arrangement direction of the display drivers first flexible wiring substrates electrically connection the display drivers to the wiring substrate, a second flexible wiring substrate extending from the wiring substrate toward an outer periphery of the display panel and a control board connected to an extended end portion of the second flexible wiring substrate and configured to control the display drivers and disposed not to overlap the display panel in a thickness direction of the display panel and having a dimension in the thickness direction of the display panel larger than that of the wiring substrate.
    Type: Application
    Filed: June 28, 2018
    Publication date: September 10, 2020
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Kazuhisa YOSHIMOTO, Kohji SAITOH, Yasuki MORI, Masaki UEHATA, Kazuya KONDOH, Kosuke KAWAMOTO
  • Patent number: 10564916
    Abstract: A liquid crystal display device includes a liquid crystal panel and a control unit. The control unit stores a plurality of setting values of a voltage applied to a counter electrode. The setting value is a value of the applied voltage at which variation in luminance appears at a portion located apart from a reference portion that is a region in the liquid crystal panel.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: February 18, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazuya Kondoh, Yasuki Mori, Masaki Uehata, Kohji Saitoh, Kazuhisa Yoshimoto, Kosuke Kawamoto
  • Publication number: 20190235336
    Abstract: [Problem] An object is to reduce crosstalk.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 1, 2019
    Inventors: MASAKI UEHATA, KOHJI SAITOH, YASUKI MORI, KAZUYA KONDOH, KAZUHISA YOSHIMOTO, KOSUKE KAWAMOTO
  • Publication number: 20190164512
    Abstract: There is provided a source driver (video signal line drive circuit) using a charge sharing system that achieves lower power consumption than a conventional case. A short-circuiting circuit short-circuits source bus lines such that a sum of numbers assigned to two source bus lines forming each set in each group is equal for all sets when it is assumed that K consecutive source bus lines (K is an even number greater than or equal to 4) form one group and numbers from 1 to K are assigned to the K source bus lines. For example, with four consecutive source bus lines forming one group, in each group, the short-circuiting circuit short-circuits the first and fourth source bus lines and short-circuits the second and third source bus lines.
    Type: Application
    Filed: May 25, 2017
    Publication date: May 30, 2019
    Inventors: KOHJI SAITOH, KOSUKE KAWAMOTO, KAZUHISA YOSHIMOTO, KAZUYA KONDOH, MASAKI UEHATA, YASUKI MORI
  • Publication number: 20190108805
    Abstract: A liquid crystal display device includes a liquid crystal panel and a control unit. The control unit stores a plurality of setting values of a voltage applied to a counter electrode. The setting value is a value of the applied voltage at which variation in luminance appears at a portion located apart from a reference portion that is a region in the liquid crystal panel.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 11, 2019
    Inventors: KAZUYA KONDOH, YASUKI MORI, MASAKI UEHATA, KOHJI SAITOH, KAZUHISA YOSHIMOTO, KOSUKE KAWAMOTO
  • Patent number: 9666140
    Abstract: The invention provides a gate-in-panel display device capable of preventing deterioration of thin-film transistors during pause drive, as well as a method for driving the same. At the end of a drive period, an active clear signal is provided to thin-film transistors in unit circuits, each thin-film transistor being connected to either a first or second node at a gate terminal, thereby bringing the thin-film transistors into ON state. As a result, the voltages of the first and second nodes are set to a reference voltage. Thus, even if a pause period lasts for a long period of time, the gate terminals of the thin-film transistors are not subjected to sustained voltage application, leading to no threshold voltage shifts.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: May 30, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Jun Nakata, Masami Ozaki, Akihisa Iwamoto, Tomohiko Nishimura, Kohji Saitoh, Masaki Uehata
  • Patent number: 9570030
    Abstract: A gate driver (24) which is provided by an IGZO-GDM and a level shifter circuit (13) are connected to each other via a first through a fifth wires (OL1 through OL5). Each wire (OL) is connected to a discharge unit (190). If an electric power supply to a first through a fifth output circuits (OC1 through OC5) in the level shifter circuit (13) becomes lower than a lower operation limit value during a power-off sequence which is supposed to remove a residual charge from inside a panel, outputs from the first through the fifth output circuits (OC1 through OC5) assume a high-impedance state, whereupon a potential on each wire (OL) is drawn by a discharge unit (190) into a ground potential. Therefore, residual charge inside the panel is removed quickly and stably when power supply is shut off.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: February 14, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akihisa Iwamoto, Masami Ozaki, Tomohiko Nishimura, Kohji Saitoh, Masaki Uehata, Jun Nakata
  • Patent number: 9530384
    Abstract: In a display device that can use a low frequency drive method, in the case of low frequency drive, in a data correction unit (23) of a display control circuit (200), a pixel grayscale value is set such that the differential value between the potential difference between the pixel electrode and the common electrode when a voltage of positive polarity is applied and the potential difference between the pixel electrode and the common electrode when a voltage of negative polarity is applied becomes larger than during normal drive. With this, a correction amount (shift amount) is made larger during low frequency drive than during normal drive, whereby flickers and ghosting during low frequency drive are prevented.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: December 27, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kohji Saitoh, Akihisa Iwamoto, Tomohiko Nishimura, Masaki Uehata, Jun Nakata, Masami Ozaki
  • Patent number: 9437154
    Abstract: Provided for each data signal line drive circuit (6a, 6b, 6c) are: a voltage generation circuit (61a, 61b, 61c) that generates a drive voltage in accordance with an external voltage; and a voltage determination circuit (63a, 63b, 63c) which determines whether or not a voltage level of at least either the external voltage or the drive voltage falls within a range of allowable voltages, in a case where the voltage level does not fall within the range of allowable voltages, operation of the voltage generation circuits (61a, 61b, 61c) being stopped.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: September 6, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Jun Nakata, Masaki Uehata, Kohji Saitoh, Masami Ozaki, Toshihiro Yanagi
  • Patent number: 9424795
    Abstract: A display device (1) includes: a scan line drive circuit (4) which line-sequentially selects from among a plurality of scan signal lines; at least one signal line drive circuit (3) which has a receiving circuit that receives a data signal, and which sequentially supplies the data signal to pixels linked to a scan signal line (6) selected by the scan line drive circuit (4); a timing controller (10) which defines, in accordance with sync signals received from an outside source, a non-scan period during which none of the scan signal lines is selected, and which transmits, to the at least one signal line drive circuit (3), an operation discriminant signal that causes the receiving circuit to be underrun during at least part of the non-scan period thus defined. The at least one signal line drive circuit (3) and the timing controller (10) are provided as separate entities.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: August 23, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kohji Saitoh, Masaki Uehata, Asahi Yamato, Masami Ozaki, Toshihiro Yanagi
  • Patent number: 9423637
    Abstract: A source AMP output circuit (10) is provided with a switching circuit (17) for carrying out the following operation. That is, in a case where a polarity is reversed, the switching circuit (17) disconnects a data signal line (S(M)) from output terminals of a positive amplifier circuit (15) and a negative polarity amplifier circuit (16) each included in the source AMP output circuit (10), and then connects the data signal line S(M) to a power supply which is in a power supply voltage range (Vdd1 to Vdd3) of the positive polarity amplifier circuit (15) or to a power supply which is in a power supply voltage range (Vdd2 to Vdd4) of the negative polarity amplifier circuit (16).
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: August 23, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kohji Saitoh, Masaki Uehata, Masami Ozaki, Toshihiro Yanagi
  • Patent number: 9355606
    Abstract: A liquid crystal display device includes: a data signal line; a scan signal line; a pixel electrode; a transistor connected to (i) the data signal line, (ii) the scan signal line, and (iii) the pixel electrode; and a common electrode, the liquid crystal display device being configured to turn on the transistor during a power-off sequence by causing a change in an electric potential of the scan signal line, the electric potential of the scan signal line reaching a first electric potential at a first timing after the change is initiated, and the common electrode being in an electrically floating state at a second timing which comes after the first timing.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 31, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kohji Saitoh, Akihisa Iwamoto, Masami Ozaki, Masaki Uehata, Jun Nakata, Tomohiko Nishimura
  • Patent number: 9240150
    Abstract: A display module of the present invention includes first through third source drivers (6-1 through 6-3) (i) which are provided for respective regions into which a display region is divided and (ii) each of which includes an analysis circuit and receives a video signal for a corresponding one of the regions but receives no video signal for the regions other than the corresponding one of the regions. The third source driver (6-3) supplies, to the first and second source drivers (6-1 and 6-2), gamma (?) setting information (19) for generating a source signal to be outputted from each of the first and second source drivers (6-1 and 6-2). The first and second source drivers (6-1 and 6-2) output respective analysis results (5a and 5b) from the respective analysis circuits. The third source driver (6-3) outputs a PWM signal (14) for controlling the light irradiation section.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: January 19, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kohji Saitoh, Masaki Uehata, Masami Ozaki
  • Patent number: 9196186
    Abstract: A display device (10) includes a timing control section (13) and a signal line drive circuit (16), either of which receives a lower power supply voltage level than the other, and a level changing circuit (20) for changing an amplitude level (T) of a reset signal (B). The timing control section (13) and the level changing circuit (20) receive the reset signal (B). The level changing circuit (20) changes the amplitude level (T) of the supplied reset signal (B) and then supply, to the signal line drive circuit (16), a reset signal (Ba) with a converted amplitude level. This makes it possible to achieve an image display with low power consumption and a stable display quality.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: November 24, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuki Takahashi, Masaki Uehata, Kohji Saitoh, Masami Ozaki, Toshihiro Yanagi
  • Publication number: 20150332650
    Abstract: Provided are a display device capable of preventing burning by suppressing occurrence of a VCOM shift which occurs when a liquid crystal panel is driven for a long period of time, and a drive method thereof. Since a source output voltage corresponding to each of tone levels from a tone value 0 to a tone value 224 agrees with a flicker regulation voltage, a shift amount from the flicker regulation voltage is set to 0 mV, and a source output voltage corresponding to a tone value 255 is obtained by further adding +40 mV as a shift amount to 4.05 V which is the flicker regulation voltage. In such a manner, a source output voltage, increased at a high tone level and in the vicinity thereof, is applied to source bus lines SL1 to SLm and written into each liquid crystal capacitance Ccl.
    Type: Application
    Filed: December 6, 2013
    Publication date: November 19, 2015
    Inventors: Kohji SAITOH, Akihisa IWAMOTO, Jun NAKATA, Masaki UEHATA, Tomohiko NISHIMURA, Ichiro UMEKAWA, Masami OZAKI
  • Publication number: 20150332632
    Abstract: The invention provides a gate-in-panel display device capable of preventing deterioration of thin-film transistors during pause drive, as well as a method for driving the same. At the end of a drive period, an active clear signal is provided to thin-film transistors in unit circuits, each thin-film transistor being connected to either a first or second node at a gate terminal, thereby bringing the thin-film transistors into ON state. As a result, the voltages of the first and second nodes are set to a reference voltage. Thus, even if a pause period lasts for a long period of time, the gate terminals of the thin-film transistors are not subjected to sustained voltage application, leading to no threshold voltage shifts.
    Type: Application
    Filed: December 6, 2013
    Publication date: November 19, 2015
    Inventors: Jun NAKATA, Masami OZAKI, Akihisa IWAMOTO, Tomohiko NISHIMURA, Kohji SAITOH, Masaki UEHATA