Abstract: An information processing apparatus (100) includes a conversion unit (102) that converts original data (110) to be edited into processed data (112) having a reduced data volume, a processed data transmission unit (104) that transmits the processed data (112) to a common processing apparatus, a reception unit (106) that receives external edited data (114) indicating editing contents, edited by the common processing apparatus on the processed data (112) from the common processing apparatus, and a composition unit (108) that reflects the editing contents obtained by the common processing apparatus in the original data (110) to be edited on the basis of the external edited data (114) received by the reception unit (106).

Abstract: An information disclosure system includes: an information disclosing unit; a setting unit; a history storage unit; and an interaction frequency calculating unit. The information disclosing unit discloses at least part of user's information as disclosure information to a communicating party. The setting unit sets a disclosure range for disclosing the user's information as the disclosure information. The history storage unit stores a history of communication between the user and the communicating party. The interaction frequency calculating unit calculates an interaction frequency between the user and the communicating party based on the history of the communication. The setting unit sets the disclosure range based on the interaction frequency calculated by the interaction frequency calculating unit.

Abstract: An information processing apparatus (100) includes a conversion unit (102) that converts original data (110) to be edited into processed data (112) having a reduced data volume, a processed data transmission unit (104) that transmits the processed data (112) to a common processing apparatus, a reception unit (106) that receives external edited data (114) indicating editing contents, edited by the common processing apparatus on the processed data (112) from the common processing apparatus, and a composition unit (108) that reflects the editing contents obtained by the common processing apparatus in the original data (110) to be edited on the basis of the external edited data (114) received by the reception unit (106).

Abstract: An information disclosure system includes: an information disclosing unit; a setting unit; a history storage unit; and an interaction frequency calculating unit. The information disclosing unit discloses at least part of user's information as disclosure information to a communicating party. The setting unit sets a disclosure range for disclosing the user's information as the disclosure information. The history storage unit stores a history of communication between the user and the communicating party. The interaction frequency calculating unit calculates an interaction frequency between the user and the communicating party based on the history of the communication. The setting unit sets the disclosure range based on the interaction frequency calculated by the interaction frequency calculating unit.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

Abstract: The information processing device which recovers a domain developing a fault caused by added application and device driver while maintaining security and reliability includes a plurality of processors, wherein the plurality of processors form a plurality of domains according to processing contents to be executed, and the processors in different domains communicate with each other through a communication unit, and which further includes a recovery unit for executing, for a domain developing a fault, failure recovery processing based on a failure recovery request notified by the domain and a recovery condition set in advance for each domain.

Abstract: A data communications processor which mediates data sending and receiving in an embedded system is provided, wherein it avoids increase of processing due to accretion of number of communication data, disuses any resources for individual management of deadline for each data, and executes deadline management without a starvation. It does not execute receiving process successively for each communication datum; however, it executes receiving process for each assembled data accumulation partial area data as a whole for each prefixed period. In addition, a plurality of data accumulation partial areas in the data accumulating means 220, which is separated for each deadline, are executed batch receiving process respectively at the period according to the relative deadline time.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

Abstract: The information processing device which recovers a domain developing a fault caused by added application and device driver while maintaining security and reliability includes a plurality of processors, wherein the plurality of processors form a plurality of domains according to processing contents to be executed, and the processors in different domains communicate with each other through a communication unit, and which further includes a recovery unit for executing, for a domain developing a fault, failure recovery processing based on a failure recovery request notified by the domain and a recovery condition set in advance for each domain.

Abstract: A biasing circuit includes an increasing circuit, a supplying circuit, a bias outputting circuit and a bias outputting circuit. The increasing circuit outputs a drive voltage, and the supplying circuit is connected in parallel to the increasing circuit and outputs a drive voltage. The bias outputting circuit outputs a bias output to a biased circuit in response to the drive voltage from the increasing circuit or the drive voltage from the supplying circuit. The control circuit controls the increasing circuit and the supplying circuit based on the bias output from the bias outputting circuit.

Abstract: There is provided a semiconductor memory device in which the trouble in reading data due to an overshoot of a data signal can be avoided even when a reference signal for giving a reference for the determination a logical value of the data signal from a memory cell is constantly generated. This semiconductor memory device is constructed such that data is read by comparing a data signal from a memory cell with a reference signal from a reference cell in a differential-type sense amplifier. The semiconductor memory device comprises a feedback circuit for limiting a relative change between the reference signal and the data signal received by the differential-type sense amplifier. This feedback circuit momentarily feeds an output of the differential-type sense amplifier back to its input node, when data stored in the memory cell is read out, to thereby momentarily render the data signal and the reference signal equal to each other.

Abstract: A biasing circuit includes an increasing circuit, a supplying circuit, a bias outputting circuit and a bias outputting circuit. The increasing circuit outputs a drive voltage, and the supplying circuit is connected in parallel to the increasing circuit and outputs a drive voltage. The bias outputting circuit outputs a bias output to a biased circuit in response to the drive voltage from the increasing circuit or the drive voltage from the supplying circuit. The control circuit controls the increasing circuit and the supplying circuit based on the bias output from the bias outputting circuit.

Abstract: A biasing circuit includes an increasing circuit, a supplying circuit, a bias outputting circuit and a bias outputting circuit. The increasing circuit outputs a drive voltage, and the supplying circuit is connected in parallel to the increasing circuit and outputs a drive voltage. The bias outputting circuit outputs a bias output to a biased circuit in response to the drive voltage from the increasing circuit or the drive voltage from the supplying circuit. The control circuit controls the increasing circuit and the supplying circuit based on the bias output from the bias outputting circuit.

Abstract: A nonvolatile memory device is provided capable of shipping after setting it as a flash memory or as a one-time memory, and which cannot be altered to a flash memory once it has been used as a one-time memory. The nonvolatile memory device of the present invention has a circuit structure such that when a nonvolatile memory receives an instruction of prohibiting erasure of internal data, the instruction is stored by setting a prescribed flag provided in the nonvolatile memory at a predetermined value, and the content of the present nonvolatile memory cannot be erased after packaging, so that it is impossible for a user to alter the values of the flag which indicates whether erasure of data is prohibited or permitted.

Abstract: A semiconductor memory device having a bit line which is precharged quickly is disclosed. According to the presenti invention, a semiconductor memory device includes a bit line which is connected to a memory cell, a first precharging circuit which precharges said bit line during a first time period, and a second precharging circuit which precharges said bit line during a second time period, wherein said first time period being longer than said second time period.

Abstract: A non-volatile semiconductor memory device is provided which is capable of shortening time required for determining a reading voltage in its reading circuit and of improving a data reading speed.

Abstract: An electrically erasable and programmable non-volatile semiconductor storage device where data is read out by comparing the output of a memory cell and the output of a reference cell by a sense amplifier. In this device, the reference cell is built so that it has a given threshold voltage value, and the gate voltage of the memory cell and the gate voltage of the reference cell are allowed to be set independently.

Abstract: In a semiconductor storage device including a differential circuit which compares a voltage outputted by a memory cell array 103 with a voltage outputted by a reference circuit 106, a constant current source circuit 109 is connected to the differential circuit 201 in parallel with the memory cell array 103 and outputs a signal for monitoring the threshold voltage of the reference circuit 106. A controller circuit 108 is changed over from an output signal of the memory cell array 103 to that of the current source circuit 109 on monitoring the reference circuit.