Patents by Inventor Masaki YAWATA

Masaki YAWATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230324208
    Abstract: A device determines the propagation time of an acoustic signal by cross-correlation analysis between a transmission signal and a reception signal. The device determines the propagation time by cross-correlation analysis between the transmission signal and the reception signal from which reverberation has yet to be removed, removes, from the reception signal, as the reverberation, a signal component at and after a time point based on the determined propagation time, and redetermines a propagation time by cross-correlation analysis between the transmission signal and the reception signal from which the reverberation has been removed.
    Type: Application
    Filed: July 20, 2021
    Publication date: October 12, 2023
    Inventors: Yoshitaka TSURUKAME, Yui ISHIDA, Masaki YAWATA
  • Publication number: 20220291026
    Abstract: A device determines a propagation time of an acoustic signal through cross-correlation analysis between a transmission signal and a reception signal. The device generates the transmission signal to satisfy (1) a ratio of a height of a peak other than a maximum peak in an autocorrelation function of the transmission signal to a height of the maximum peak being 0.8 or less and (2) a duration of the transmission signal being at least five times a shortest period of the transmission signal or at least 20 times a half width at half maximum of the autocorrelation function of the transmission signal.
    Type: Application
    Filed: September 25, 2020
    Publication date: September 15, 2022
    Inventors: Naoki YOSHITAKE, Yui ISHIDA, Takeshi FUJIWARA, Yoshitaka TSURUKAME, Masaki YAWATA
  • Publication number: 20220294183
    Abstract: A drive circuit includes a GaN FET having a source connected to an anode of an LD and a drain connected to a power source of the LD, a gate drive having an output port connected to a gate of the GaN FET and a negative voltage port connected to the source of the GaN FET to receive an input voltage at a positive voltage port and output the input voltage from the output port in response to a signal with a predetermined level, a capacitor between the positive and negative voltage ports of the gate drive, a diode on a power source line connecting the positive voltage port of the gate drive and a VDD power source for outputting a voltage less than the breakdown voltage at a voltage Vgs of the GaN FET, and a semiconductor switch between the source of the GaN FET and the ground.
    Type: Application
    Filed: July 28, 2020
    Publication date: September 15, 2022
    Inventors: Masaki YAWATA, Chihiro MIYAHARA