Abstract: An A/D converter includes an A/D conversion circuit, a multiplying D/A converter, a switch circuit, and a control circuit. The control circuit prevents an A/D output of the A/D conversion circuit from being input to the D/A converter and controls the switch circuit so that an input voltage to be A/D-converted is recycled through the switch circuit and the multiplying D/A converter. As a result, the input voltage is amplified to a suitable level for A/D conversion. Then, the control circuit allows the A/D output to be inputted to the D/A converter and controls the switch circuit so that the amplified voltage is recycled through the switch circuit, the multiplying D/A converter, and the A/D conversion circuit. As a result, the amplified voltage is A/D-converted.

Abstract: A multi-channel sample and hold circuit includes an operational amplifier, plural electric charge setting channels. Each of the electric charge setting channels includes an input terminal, an electric charge setting capacitor, an electric charge setting switch connected between the input terminal and the electric charge setting capacitor, a channel separating switch connected between the electric charge setting capacitor and the input terminal of the operational amplifier and a holding switch and a control circuit for selecting one of the electric charge setting channels to hold a signal that is inputted to the input terminal thereof.

Abstract: An A/D converter includes an A/D conversion circuit, a multiplying D/A converter, a switch circuit, and a control circuit. The control circuit prevents an A/D output of the A/D conversion circuit from being input to the D/A converter and controls the switch circuit so that an input voltage to be A/D-converted is recycled through the switch circuit and the multiplying D/A converter. As a result, the input voltage is amplified to a suitable level for A/D conversion. Then, the control circuit allows the A/D output to be inputted to the D/A converter and controls the switch circuit so that the amplified voltage is recycled through the switch circuit, the multiplying D/A converter, and the A/D conversion circuit. As a result, the amplified voltage is A/D-converted.

Abstract: In a comparing circuit, an input signal switching circuit has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The input signal switching circuit is configured to receive a first input signal inputted to the first input terminal and a second input signal inputted to the second input terminal. The input signal switching circuit is also configured to output the first input signal to switchably one of the first and second output terminals and the second input signal to other thereof in accordance with a switching signal. A comparator has a reverse input terminal and a non-reverse input terminal and configured to receive through the reverse input terminal a first signal outputted from the first output terminal, and receive through the non-reverse input terminal a second signal outputted from the second output terminal.

Abstract: The A/D converter has first and second PPDC circuits (pulse-phase-difference coding circuits). The first PPDC circuit performs A/D conversions on the reference voltage and on the voltage signal amplified by an amplifier in an alternating sequence, the amplifier using the reference voltage as a potential base thereof. The second PPDC circuit performs A/D conversions always on the reference voltage. The A/D-converted data set of the voltage signal outputted from the first PPDC circuit is corrected depending on the difference between the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the reference voltage and the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the voltage signal.

Abstract: The A/D converter has first and second PPDC circuits (pulse-phase-difference coding circuits). The first PPDC circuit performs A/D conversions on the reference voltage and on the voltage signal amplified by an amplifier in an alternating sequence, the amplifier using the reference voltage as a potential base thereof. The second PPDC circuit performs A/D conversions always on the reference voltage. The A/D-converted data set of the voltage signal outputted from the first PPDC circuit is corrected depending on the difference between the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the reference voltage and the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the voltage signal.

Abstract: In a comparing circuit, an input signal switching circuit has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The input signal switching circuit is configured to receive a first input signal inputted to the first input terminal and a second input signal inputted to the second input terminal. The input signal switching circuit is also configured to output the first input signal to switchably one of the first and second output terminals and the second input signal to other thereof in accordance with a switching signal. A comparator has a reverse input terminal and a non-reverse input terminal and configured to receive through the reverse input terminal a first signal outputted from the first output terminal, and receive through the non-reverse input terminal a second signal outputted from the second output terminal.

Abstract: In a comparing circuit, an input signal switching circuit has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The input signal switching circuit is configured to receive a first input signal inputted to the first input terminal and a second input signal inputted to the second input terminal. The input signal switching circuit is also configured to output the first input signal to switchably one of the first and second output terminals and the second input signal to other thereof in accordance with a switching signal. A comparator has a reverse input terminal and a non-reverse input terminal and configured to receive through the reverse input terminal a first signal outputted from the first output terminal, and receive through the non-reverse input terminal a second signal outputted from the second output terminal.

Abstract: An object of the present invention is to obtain a high A/D or D/A conversion accuracy, even when there exists a slope in the insulating layer film thickness distribution of the capacitors. The DAC comprises: a capacitor array for storing electric charges in accordance with a digital voltage signal; and an operational amplifier of which input terminal is connected with the capacitor array and amplifies a voltage which corresponds to the electric charges. Here, the capacitor array comprises a plurality of unit capacitors which comprises 2n divisional capacitors which are of the same shape and are connected in parallel. The divisional capacitors are linearly disposed in mirror symmetry about a center line of the capacitor array and one half of the divisional capacitors every unit capacitor is disposed at one side of the center line and another half is disposed at the another side of the center line.

Abstract: An object of the present invention is to obtain a high A/D or D/A conversion accuracy, even when there exists a slope in the insulating layer film thickness distribution of the capacitors. The DAC comprises: a capacitor array for storing electric charges in accordance with a digital voltage signal; and an operational amplifier of which input terminal is connected with the capacitor array and amplifies a voltage which corresponds to the electric charges. Here, the capacitor array comprises a plurality of unit capacitors which comprises 2n divisional capacitors which are of the same shape and are connected in parallel. The divisional capacitors are linearly disposed in mirror symmetry about a center line of the capacitor array and one half of the divisional capacitors every unit capacitor is disposed at one side of the center line and another half is disposed at the another side of the center line.

Abstract: A voltage detection circuit detects a regulator output voltage. A current detection circuit detects a regulator output current. A first amplifier circuit generates a voltage error signal in response to a command output voltage level indicative of a target value of the regulator output voltage, and in response to the detected regulator output voltage. A second amplifier circuit generates a current limiting signal in response to a command limit current level indicative of a limit value of the regulator output current, and in response to the detected regulator output current. A device controls the regulator output current in response to a control current. A first transistor provided in a flow path for the control current is driven in response to the voltage error signal. A second transistor provided in the flow path and connected in series with the first transistor is driven in response to the current limiting signal.

Abstract: In a comparing circuit, an input signal switching circuit has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The input signal switching circuit is configured to receive a first input signal inputted to the first input terminal and a second input signal inputted to the second input terminal. The input signal switching circuit is also configured to output the first input signal to switchably one of the first and second output terminals and the second input signal to other thereof in accordance with a switching signal. A comparator has a reverse input terminal and a non-reverse input terminal and configured to receive through the reverse input terminal a first signal outputted from the first output terminal, and receive through the non-reverse input terminal a second signal outputted from the second output terminal.

Abstract: An operational amplifier includes a differential amplification circuit, a voltage amplification circuit, a capacitor, and a bias setting circuit. The differential amplification circuit includes load transistors arranged in a cascode connection. The voltage amplification circuit forms a stage following the differential amplification circuit. The capacitor couples the differential amplification circuit and the voltage amplification circuit with each other. The bias setting circuit charges the capacitor to a prescribed bias voltage before amplification is started. Preferably, the charged capacitor sets the differential amplification circuit in a prescribed biased state.

Abstract: A voltage detection circuit detects a regulator output voltage. A current detection circuit detects a regulator output current. A first amplifier circuit generates a voltage error signal in response to a command output voltage level indicative of a target value of the regulator output voltage, and in response to the detected regulator output voltage. A second amplifier circuit generates a current limiting signal in response to a command limit current level indicative of a limit value of the regulator output current, and in response to the detected regulator output current. A device controls the regulator output current in response to a control current. A first transistor provided in a flow path for the control current is driven in response to the voltage error signal. A second transistor provided in the flow path and connected in series with the first transistor is driven in response to the current limiting signal.

Abstract: An operational amplifier includes a differential amplification circuit, a voltage amplification circuit, a capacitor, and a bias setting circuit. The differential amplification circuit includes load transistors arranged in a cascode connection. The voltage amplification circuit forms a stage following the differential amplification circuit. The capacitor couples the differential amplification circuit and the voltage amplification circuit with each other. The bias setting circuit charges the capacitor to a prescribed bias voltage before amplification is started. Preferably, the charged capacitor sets the differential amplification circuit in a prescribed biased state.

Abstract: After a second (i.e., 2nd-step) A/D conversion code n2 is produced from an A/D conversion circuit 1, a switch S10 is turned off and a switch S11 is turned on so that an operational amplifier 3 and a capacitor CF cooperate as a hold circuit. Arrayed capacitors C0 to C7 are charged based on an output voltage of the operational amplifier 3. Next, switches S11 and S12 are turned off and switches S13 to S15 are turned on to initialize the electric charge of the capacitor CF to 0 and to charge a capacitor CIN to a predetermined level (=V1+VOFF), wherein VOFF is an offset voltage of the operational amplifier 3. Subsequently, switches S13 to S15 are turned off and the switch S12 is turned on. Then, the switch S10 is turned on and switches S0 to S7 are shifted to a reference voltage terminal 2 or to a ground terminal GND, thereby implementing charge redistribution.

Abstract: A buffer circuit includes a signal input terminal and a signal output terminal. A first operational amplifier includes a differential amplifier circuit having an input transistor of an N-channel MOS type. The first operational amplifier has an inverting input terminal and an output terminal connected to each other. The first operational amplifier has a non-inverting input terminal connected to the signal input terminal. A second operational amplifier includes a differential amplifier circuit having an input transistor of a P-channel MOS type. The second operational amplifier has an inverting input terminal and an output terminal connected to each other. The second operational amplifier has a non-inverting input terminal connected to the signal input terminal.

Abstract: An offset voltage correction circuit for an operational amplifier (1) includes an offset voltage varying device (16, 17, 20, 21-23) for varying an offset voltage in the operational amplifier (1) in response to an offset voltage control value. A comparing device (25) operates for comparing an output voltage from the operational amplifier (1) with a prescribed reference voltage. A control device (19, 300) operates for outputting the offset voltage control value to the offset voltage varying device, for changing the offset voltage control value, for storing, in response to a result of the comparing by the comparing device (25), a digital signal representative of the offset voltage control value at which the output voltage from the operational amplifier (1) and the prescribed reference voltage are equal, and for correcting the offset voltage in the operational amplifier (1) in response to the stored digital signal.

Abstract: A waveform shaping apparatus includes a comparing device for comparing a sensor output signal with a threshold voltage to convert the sensor output signal into a waveform shaped signal. The comparing device outputs the waveform shaped signal. The waveform shaping apparatus also includes a frequency-to-voltage converting device for generating the threshold voltage in response to a frequency of the output signal from the comparing device. In the frequency-to-voltage converting device, a clock signal is generated in response to the output signal from the comparing device. The clock signal has a period proportional to a period of the output signal from the comparing device. A counting device is operative for counting pulses in the clock signal generated by the clock signal generating device for every given period, and outputting a signal representing a counted pulse number depending on the frequency of the output signal from the comparing device.

Abstract: An input voltage Va and a threshold voltage Vc are compared in a comparator 21 to shaping the waveform of a sensor signal. The period of the output signal of comparator 21 is measured by a period measuring circuit 4. A stepped waveform voltage generating circuit 5 generates a stepped waveform voltage based on the measured period. The stepped waveform voltage is converted into corresponding current in a V-I conversion circuit 6. The current of V-I conversion circuit 6 is supplied to a resistance 23d or 23e via an analog switch 22a or 22b which turns on or off in response to the operation of comparator 21, thereby applying a stepped offset voltage to input voltage Va threshold voltage Vc to perform the hysteresis operation.