Patents by Inventor Masako Kodera

Masako Kodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10799917
    Abstract: A substrate processing apparatus removes foreign substances from a substrate at high removal efficiency. The substrate processing apparatus includes: a scrubber to perform surface processing of the substrate by bringing a scrubbing member into sliding contact with a first surface of the substrate, a hydrostatic support mechanism for supporting a second surface of the substrate via fluid pressure without contacting the substrate, the second surface being an opposite surface of the first surface, a cleaner to clean the processed substrate, and a dryer to dry the cleaned substrate. The scrubber brings the scrubbing member into sliding contact with the first surface while rotating the scrubbing member about a central axis of the scrubber.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 13, 2020
    Assignees: EBARA CORPORATION, Toshiba Memory Corporation
    Inventors: Yu Ishii, Hiroyuki Kawasaki, Kenichi Nagaoka, Kenya Ito, Masako Kodera, Hiroshi Tomita, Takeshi Nishioka
  • Patent number: 10692206
    Abstract: A crystal analysis apparatus includes a first storage unit storing a crystal lattice image of a crystal region of a sample and a reference crystal lattice image for the crystal region of the sample. A first image processing unit is configured to generate a moiré image from the crystal lattice image and the reference crystal lattice image. A second storage unit stores a predetermined correspondence relationship between a moiré fringe pattern in the moiré image and a crystal defect in the crystal region or a predetermined correspondence relationship between the moiré fringe pattern in the moiré image and a crystal strain in the crystal region. An analysis unit is configured to compare the moiré fringe pattern in the moiré image to predetermined correspondence relationships stored in the second storage unit.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: June 23, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Masako Kodera
  • Patent number: 10586694
    Abstract: According to one embodiment, a method for fabricating a semiconductor device includes performing a back surface processing to remove at least one of a scratch and a foreign material formed on a back surface of a substrate to be processed, a front surface of the substrate being retained in a non-contact state, contacting the back surface of the substrate to a stage to be retained, and providing a pattern on the front surface of the substrate by using lithography.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 10, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masako Kodera, Hiroshi Tomita, Takeshi Nishioka
  • Publication number: 20190262870
    Abstract: A substrate processing apparatus removes foreign substances from a substrate at high removal efficiency. The substrate processing apparatus includes: a scrubber to perform surface processing of the substrate by bringing a scrubbing member into sliding contact with a first surface of the substrate, a hydrostatic support mechanism for supporting a second surface of the substrate via fluid pressure without contacting the substrate, the second surface being an opposite surface of the first surface, a cleaner to clean the processed substrate, and a dryer to dry the cleaned substrate. The scrubber brings the scrubbing member into sliding contact with the first surface while rotating the scrubbing member about a central axis of the scrubber.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Yu Ishii, Hiroyuki Kawasaki, Kenichi Nagaoka, Kenya Ito, Masako Kodera, Hiroshi Tomita, Takeshi Nishioka
  • Publication number: 20190262869
    Abstract: A substrate processing apparatus removes foreign substances from a substrate at high removal efficiency. The substrate processing apparatus includes: a scrubber to perform surface processing of the substrate by bringing a scrubbing member into sliding contact with a first surface of the substrate, a hydrostatic support mechanism for supporting a second surface of the substrate via fluid pressure without contacting the substrate, the second surface being an opposite surface of the first surface, a cleaner to clean the processed substrate, and a dryer to dry the cleaned substrate. The scrubber brings the scrubbing member into sliding contact with the first surface while rotating the scrubbing member about a central axis of the scrubber.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Yu Ishii, Hiroyuki Kawasaki, Kenichi Nagaoka, Kenya Ito, Masako Kodera, Hiroshi Tomita, Takeshi Nishioka
  • Patent number: 10328465
    Abstract: A substrate processing apparatus removes foreign substances from a substrate at high removal efficiency. The substrate processing apparatus includes: a scrubber to perform surface processing of the substrate by bringing a scrubbing member into sliding contact with a first surface of the substrate, a hydrostatic support mechanism for supporting a second surface of the substrate via fluid pressure without contacting the substrate, the second surface being an opposite surface of the first surface, a cleaner to clean the processed substrate, and a dryer to dry the cleaned substrate. The scrubber brings the scrubbing member into sliding contact with the first surface while rotating the scrubbing member about a central axis of the scrubber.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: June 25, 2019
    Assignee: EBARA CORPORATION
    Inventors: Yu Ishii, Hiroyuki Kawasaki, Kenichi Nagaoka, Kenya Ito, Masako Kodera, Hiroshi Tomita, Takeshi Nishioka
  • Patent number: 10256314
    Abstract: A semiconductor device includes a first semiconductor layer, a first electrode above and electrically connected to the first semiconductor layer, a second electrode above the first semiconductor layer and electrically connected to the first semiconductor layer, a first insulating layer above the first semiconductor layer between the first and second electrodes, and a third electrode. The second electrode is spaced from the first electrode along the first semiconductor layer. The third electrode includes a first portion above the first insulating layer between the first and second electrodes, and a second portion between the first portion and the second electrode and extending from the first portion in the direction of, and spaced from, the second electrode. The distance between the first semiconductor layer and an adjacent curved surface of the second portion gradually increases from the first portion to the end of the second portion distal the first portion.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: April 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Kodera, Tomoko Matsudai
  • Publication number: 20190005635
    Abstract: A crystal analysis apparatus includes a first storage unit storing a crystal lattice image of a crystal region of a sample and a reference crystal lattice image for the crystal region of the sample. A first image processing unit is configured to generate a moiré image from the crystal lattice image and the reference crystal lattice image. A second storage unit stores a predetermined correspondence relationship between a moiré fringe pattern in the moiré image and a crystal defect in the crystal region or a predetermined correspondence relationship between the moiré fringe pattern in the moiré image and a crystal strain in the crystal region. An analysis unit is configured to compare the moiré fringe pattern in the moiré image to predetermined correspondence relationships stored in the second storage unit.
    Type: Application
    Filed: February 26, 2018
    Publication date: January 3, 2019
    Inventor: Masako KODERA
  • Patent number: 9937602
    Abstract: In a substrate processing method according to an embodiment, a surface of an object to be polished disposed on a substrate is polished on a polishing pad supplied with slurry. After the polishing process using the slurry, the surface of the object to be polished on the polishing pad is polished, while supplying water on the polishing pad where a residue including the slurry or a sludge of the polishing pad adhered. After the polishing process using the water, the surface of the object to be polished is cleaned on the polishing pad by supplying rinse liquid on the polishing pad.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: April 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yosuke Otsuka, Masako Kodera, Yukiteru Matsui
  • Publication number: 20180097096
    Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a bandgap larger than a bandgap of the first nitride semiconductor layer, a gate electrode provided on the first nitride semiconductor layer, a first electrode provided on the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a second electrode provided on the first nitride semiconductor layer, electrically connected to the first nitride semiconductor layer, and located between the first electrode and the second electrode, a first aluminum nitride layer that provided between the gate electrode and the second electrode, and provided on the second nitride semiconductor layer, and a second aluminum nitride layer provided on the first aluminum nitride layer. The first aluminum nitride layer is crystalline. The second aluminum nitride layer is non-crystalline.
    Type: Application
    Filed: March 3, 2017
    Publication date: April 5, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toru SUGIYAMA, Masako KODERA, Kunio TSUDA
  • Publication number: 20170263724
    Abstract: A semiconductor device includes a first semiconductor layer, a first electrode above and electrically connected to the first semiconductor layer, a second electrode above the first semiconductor layer and electrically connected to the first semiconductor layer, a first insulating layer above the first semiconductor layer between the first and second electrodes, and a third electrode. The second electrode is spaced from the first electrode along the first semiconductor layer. The third electrode includes a first portion above the first insulating layer between the first and second electrodes, and a second portion between the first portion and the second electrode and extending from the first portion in the direction of, and spaced from, the second electrode. The distance between the first semiconductor layer and an adjacent curved surface of the second portion gradually increases from the first portion to the end of the second portion distal the first portion.
    Type: Application
    Filed: August 26, 2016
    Publication date: September 14, 2017
    Inventors: Masako KODERA, Tomoko MATSUDAI
  • Publication number: 20160375547
    Abstract: In a substrate processing method according to an embodiment, a surface of an object to be polished disposed on a substrate is polished on a polishing pad supplied with slurry. After the polishing process using the slurry, the surface of the object to be polished on the polishing pad is polished, while supplying water on the polishing pad where a residue including the slurry or a sludge of the polishing pad adhered. After the polishing process using the water, the surface of the object to be polished is cleaned on the polishing pad by supplying rinse liquid on the polishing pad.
    Type: Application
    Filed: September 9, 2016
    Publication date: December 29, 2016
    Inventors: Yosuke OTSUKA, Masako KODERA, Yukiteru MATSUI
  • Publication number: 20160358768
    Abstract: According to one embodiment, a method for fabricating a semiconductor device includes performing a back surface processing to remove at least one of a scratch and a foreign material formed on a back surface of a substrate to be processed, a front surface of the substrate being retained in a non-contact state, contacting the back surface of the substrate to a stage to be retained, and providing a pattern on the front surface of the substrate by using lithography.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Inventors: Masako KODERA, Hiroshi TOMITA, Takeshi NISHIOKA
  • Publication number: 20160035598
    Abstract: According to one embodiment, a method for chemical planarization includes: preparing a treatment liquid containing a hydrosilicofluoric acid aqueous solution containing silicon dioxide dissolved therein at a saturated concentration; and decreasing height of irregularity of a silicon dioxide film. In the decreasing, dissolution rate of convex portions is made larger than dissolution rate of concave portion of the irregularity while changing equilibrium state of the treatment liquid at areas being in contact with the convex portions of the irregularity, in a state in which the silicon dioxide film having the irregularity is brought into contact with the treatment liquid.
    Type: Application
    Filed: October 16, 2015
    Publication date: February 4, 2016
    Inventors: Masako Kodera, Yukiteru Matsui
  • Patent number: 9196501
    Abstract: According to one embodiment, a method for chemical planarization includes: preparing a treatment liquid containing a hydrosilicofluoric acid aqueous solution containing silicon dioxide dissolved therein at a saturated concentration; and decreasing height of irregularity of a silicon dioxide film. In the decreasing, dissolution rate of convex portions is made larger than dissolution rate of concave portion of the irregularity while changing equilibrium state of the treatment liquid at areas being in contact with the convex portions of the irregularity, in a state in which the silicon dioxide film having the irregularity is brought into contact with the treatment liquid.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: November 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Kodera, Yukiteru Matsui
  • Publication number: 20150290765
    Abstract: In a substrate processing method according to an embodiment, a surface of an object to be polished disposed on a substrate is polished on a polishing pad supplied with slurry. After the polishing process using the slurry, the surface of the object to be polished on the polishing pad is polished, while supplying water on the polishing pad where a residue including the slurry or a sludge of the polishing pad adhered. After the polishing process using the water, the surface of the object to be polished is cleaned on the polishing pad by supplying rinse liquid on the polishing pad.
    Type: Application
    Filed: March 11, 2015
    Publication date: October 15, 2015
    Inventors: Yosuke OTSUKA, Masako KODERA, Yukiteru MATSUI
  • Publication number: 20140187042
    Abstract: According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.
    Type: Application
    Filed: March 6, 2014
    Publication date: July 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Masako Kodera, Hiroshi Tomita, Gaku Minamihaba, Akifumi Gawase
  • Patent number: 8754433
    Abstract: According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Gaku Minamihaba, Hajime Eda, Masayoshi Iwayama, Minoru Amano, Masatoshi Yoshikawa, Motoyuki Sato, Kyoichi Suguro, Masako Kodera
  • Patent number: 8740667
    Abstract: According to one embodiment, a polishing method comprises pressing a substrate being rotated against a polishing pad being rotated and supplying slurry on the polishing pad, measuring a surface temperature of the polishing pad, and when the surface temperature is not less than a predetermined temperature, jetting jet stream containing supercooled droplets from a nozzle having a narrow portion toward the polishing pad.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Kodera, Yukiteru Matsui
  • Patent number: 8703004
    Abstract: According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Masako Kodera, Hiroshi Tomita, Gaku Minamihaba, Akifumi Gawase