Patents by Inventor Masako Nakano

Masako Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220348864
    Abstract: [Problem] To provide a cell preparation including mesenchymal stem cells (MSCs) having a high therapeutic effect. [Solution] A method for producing activated mesenchymal stem cells, including a step of culturing MSCs in a medium containing an activator that includes an extract from a mammalian fetal appendage as an active ingredient, using a cell culture carrier having a three-dimensional structure formed of a fiber is provided. A marker for a therapeutic effect of MSCs selected from the group consisting of p16ink4a, p14ARF, CDK4, CDK6, RB, and CD47, a method for determining a therapeutic effect using the marker, a method for determining suitability of MSCs to be treated with a treatment for enhancing a therapeutic effect of MSCs, a cell preparation including MSCs, and a method for producing the same are also provided.
    Type: Application
    Filed: June 9, 2022
    Publication date: November 3, 2022
    Applicant: Sapporo Medical University
    Inventors: Takako Chikenji, Mineko Fujimiya, Yuki Saito, Masako Nakano, Miho Otani, Yuka Mizue, Takashi Matsumura, Kozue Kamiya
  • Publication number: 20210369918
    Abstract: A cell sheet for transplantation into a living body, containing MSCs having an average cell density of 3.0×104 cells/cm2 or less on the surface of the sheet is provided. A method for producing a cell sheet for transplantation into a living body, including: a step of seeding MSCs on a cell culture carrier having a three-dimensional structure formed of fibers at a cell number of 3.0×105 cells/cm2 or less; and a step of culturing the MSCs and thereby preparing a cell sheet containing the MSCs having an average cell density of 3.0×104 cells/cm2 or less is also provided.
    Type: Application
    Filed: April 25, 2019
    Publication date: December 2, 2021
    Applicant: Sapporo Medical University
    Inventors: Takako CHIKENJI, Mineko FUJIMIYA, Yuki SAITO, Masako NAKANO, Naoto Konari, Miho OTANI
  • Publication number: 20200131470
    Abstract: [Problem] To provide a cell preparation including mesenchymal stem cells (MSCs) having a high therapeutic effect. [Solution] A method for producing activated mesenchymal stem cells, including a step of culturing MSCs in a medium containing an activator that includes an extract from a mammalian fetal appendage as an active ingredient, using a cell culture carrier having a three-dimensional structure formed of a fiber is provided. A marker for a therapeutic effect of MSCs selected from the group consisting of p16ink4a, p14ARF, CDK4, CDK6, RB, and CD47, a method for determining a therapeutic effect using the maker, a method for determining suitability of MSCs to be treated with a treatment for enhancing a therapeutic effect of MSCs, a cell preparation including MSCs, and a method for producing the same are also provided.
    Type: Application
    Filed: April 25, 2018
    Publication date: April 30, 2020
    Applicant: Sapporo Medical University
    Inventors: Takako CHIKENJI, Mineko FUJIMIYA, Yuki SAITO, Masako NAKANO, Miho OTANI, Yuka MIZUE, Takashi MATSUMURA, Kozue KAMIYA
  • Patent number: 5394352
    Abstract: A carry lookahead circuit for an operation circuit having arithmetic units includes an AND gate and an OR gate for each arithmetic unit. A lookahead carry signal to be inputted to a third arithmetic unit of the operation circuit is the output of the OR gate or the logical sum of the output of the AND gate, which is the logical product of the lookahead carry signal from the OR gate to be inputted to a second arithmetic unit and the carry condition output of the second arithmetic unit, and the carry output signal of the second arithmetic unit. This arrangement can reduce the number of AND gates used in the conventional carry lookahead circuit by two (by(m-3) for m arithmetic units) and will make possible the reduction of the chip-occupying area of the structural elements and the load capacitances of signal transfer paths in the circuit.
    Type: Grant
    Filed: February 18, 1993
    Date of Patent: February 28, 1995
    Assignee: NEC Corporation
    Inventor: Masako Nakano
  • Patent number: 5020016
    Abstract: A zero detection circuit operates to detect whether or not the result of addition/subtraction between a pair of binary numbers each composed of a plurality of bits becomes zero in all the plurality of bits. The zero detection circuit comprises a logic circuit receiving the pair of binary numbers A and B for generating a zero discrimination signal when anyone of the following four conditions is satisfied for each pair of bits of the same digit of the pair of binary numbers A and B:a first condition: if (Ai, Bi)=(0,0), (A.sup.i+1, B.sup.i+1)=(0,0);a second condition: if (Ai, Bi)=(0,0), (A.sup.i+1, B.sup.i+1)=(1,1);a third condition: if (Ai, Bi)=(1,1), (A.sup.i+1, B.sup.i+1)=0,1) or (1,0); anda fourth condition; if (Ai, Bi)=(1,0) or (0,1), (A.sup.i+1, B.sup.i+1)=(1,0) or (0,1)where i is a natural number indicative of the digit place of the pair of binary numbers A and B.
    Type: Grant
    Filed: May 1, 1989
    Date of Patent: May 28, 1991
    Assignee: NEC Corporation
    Inventors: Masako Nakano, Yutaka Yamagami