Abstract: A driver IC has a rectangular shape, and includes a first input terminal group in which first input terminals are disposed at intervals along a first long side, that is opposite a side that faces a display section, from a first short side. A second input terminal group is provided in which second input terminals are disposed at intervals along a second long side that faces the display section, from the first short side. An output terminal group is provided in which output terminals that output signals to the display section are disposed at intervals along the second long side from a position, which is spaced apart for a predetermined distance from where the second input terminals are disposed, to a second short side. A terminal group is not provided at positions that oppose the output terminal group at the first long side.

Abstract: A driver IC has a rectangular shape, and includes a first input terminal group in which first input terminals are disposed at intervals along a first long side, that is opposite a side that faces a display section, from a first short side. A second input terminal group is provided in which second input terminals are disposed at intervals along a second long side that faces the display section, from the first short side. An output terminal group is provided in which output terminals that output signals to the display section are disposed at intervals along the second long side from a position, which is spaced apart for a predetermined distance from where the second input terminals are disposed, to a second short side. A terminal group is not provided at positions that oppose the output terminal group at the first long side.

Abstract: The present invention provides a display panel including: a first input terminal group in which input terminals are disposed at intervals along first long side of a rectangular driver IC facing a panel end portion; a second input terminal group in which input terminals are disposed at intervals along the second long side of the driver IC facing a display section; a first wiring group connected to the first input terminal group, that extends under the first short side of the driver IC and extends out from between the driver IC and the panel body; and a second wiring group connected to the second input terminal group, that passes under the second long side of the driver IC and extends out from between the driver IC and the panel body.

Abstract: A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.

Abstract: A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.

Abstract: A semiconductor integrated circuit has an output terminal connected to an external load, an internal signal line by which the output terminal is connected to an internal node, and a voltage generator that outputs a voltage to the internal node, for output through the internal signal line and the output terminal to the external load. A voltage attenuating element is connected to the internal signal line to attenuate voltage swings on the internal signal line. A limiting circuit is connected to the internal node to limit the voltage at the internal node to a predetermined range. Moderate voltage swings caused by external electromagnetic interference are kept within the predetermined range by the voltage attenuating element, so that the limiting circuit does not operate and the average output voltage is not changed.

Abstract: A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.

Abstract: A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.

Abstract: A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.

Abstract: The present invention provides a display panel including: a first input terminal group in which input terminals are disposed at intervals along first long side of a rectangular driver IC facing a panel end portion; a second input terminal group in which input terminals are disposed at intervals along the second long side of the driver IC facing a display section; a first wiring group connected to the first input terminal group, that extends under the first short side of the driver IC and extends out from between the driver IC and the panel body; and a second wiring group connected to the second input terminal group, that passes under the second long side of the driver IC and extends out from between the driver IC and the panel body.

Abstract: A semiconductor integrated circuit has an output terminal connected to an external load, an internal signal line by which the output terminal is connected to an internal node, and a voltage generator that outputs a voltage to the internal node, for output through the internal signal line and the output terminal to the external load. A voltage attenuating element is connected to the internal signal line to attenuate voltage swings on the internal signal line. A limiting circuit is connected to the internal node to limit the voltage at the internal node to a predetermined range. Moderate voltage swings caused by external electromagnetic interference are kept within the predetermined range by the voltage attenuating element, so that the limiting circuit does not operate and the average output voltage is not changed.

Abstract: A semiconductor integrated circuit includes a first voltage generating circuit which generates a boosted voltage based on a first external power supply voltage. The boosted voltage is greater than the first external power supply voltage. The semiconductor integrated circuit further includes a second voltage generating circuit which generates first and second converted output voltages which are different than the boosted voltage and each other. The second voltage generating circuit generates the first converted output voltage based on the first external power supply voltage. The second voltage generating circuit generates the second converted output voltage based on the boosted voltage after the first converted output voltage is generated.

Abstract: A semiconductor integrated circuit includes a first voltage generating circuit which generates a boosted voltage based on a first external power supply voltage. The boosted voltage is greater than the first external power supply voltage. The semiconductor integrated circuit further includes a second voltage generating circuit which generates first and second converted output voltages which are different than the boosted voltage and each other. The second voltage generating circuit generates the first converted output voltage based on the first external power supply voltage. The second voltage generating circuit generates the second converted output voltage based on the boosted voltage after the first converted output voltage is generated.

Abstract: A semiconductor memory device includes a pair of bit lines; a first sense amplifier coupled to the pair of bit lines; and a first controller, which controls the first sense amplifier. The first sense amplifier includes a flip-flop circuit having a pair of NMOS transistors and a pair of PMOS transistors; a first transistor connected to a source terminal of the NMOS transistors in the flip-flop circuit; and a second transistor connected to a source terminal of the PMOS transistors in the flip-flop circuit. The first controller includes a first NOR circuit, having input terminals to which a write command signal and a sense amplifier driving signal are supplied and having an output terminal connected to a gate of the first transistor.

Abstract: An arbiter circuit minimizes the occurrence of malfunctions and permits easy adjustment. The arbiter circuit includes a data transfer request signal holding device for accepting a plurality of data transfer request signals and holding the data transfer request signals in response to predetermined timing signals, a prioritizing device for determining only a signal with the highest priority at a certain point as a valid signal and the signals with lower priorities as invalid signals in order to assign priorities to output signals from the data transfer request signal holding device, and a delaying device for generating data transfer execution signals from the output signals of the prioritizing device. This arrangement restrains the occurrence of errors in assigning priorities to data transfer request signals and permits easy priority timing setting, thus allowing easy adjustment of a circuit to be achieved.

Abstract: A semiconductor memory device includes: a pair of bit lines; a first sense amplifier coupled to the pair of bit lines; and a first controller, which controls the first sense amplifier. The first sense amplifier comprises a flip-flop circuit having a pair of NMOS transistors and a pair of PMOS transistors; a first transistor connected to a source terminal of the NMOS transistors in the flip-flop circuit; and a second transistor connected to a source terminal of the PMOS transistors in the flip-flop circuit. The first controller comprises a first NOR circuit, comprising input terminals to which a write command signal and a sense amplifier driving signal are supplied and an output terminal connected to a gate of the first transistor.

Abstract: Switching is provided such that the bit lines between a sense amp and the memory cells connected to the sense amp are put into a non-conducting state during normal operation, and are put into a conducting state during characteristic tests. A control circuit is provided which outputs control signals to control the conducting state of this switching. The control circuit has a signal generation unit and a control signal switching unit. The signal generation unit generates driving signals and the inverted signals of these driving signals in order to drive the control circuit using applied voltages from outside. The control signal switching unit includes a plurality of transmission gates, and outputs control signals according to memory cell select signals and the inverted signals of same, based on the combination of conducting and non-conducting states of the transmission gates, which depend on the supply of driving signals and inverted driving signals.

Abstract: Switching means are provided such that the bit lines between a sense amp and the memory cells connected to the sense amp are put into a non-conducting state during normal operation, and are put into a conducting state during characteristic tests. A control circuit is provided which outputs control signals to control the conducting state of this switching means. The control circuit has a signal generation unit and a control signal switching unit. The signal generation unit generates driving signals and the inverted signals of these driving signals in order to drive the control circuit using applied voltages from outside. The control signal switching unit comprises a plurality of transmission gates, and outputs control signals according to memory cell select signals and the inverted signals of same, based on the combination of conducting and non-conducting states of the transmission gates, which depend on the supply of driving signals and inverted driving signals.

Abstract: A new and improved semiconductor memory that facilitates machining of iterated circuits and solves the problems of the prior art such as the lengthy machining process, the compromised machining accuracy and the considerable time required for device evaluation is provided. A semiconductor memory 10 is provided with a plurality of output circuits 11 and a fuse circuit 12 connected to each of the output circuits. The fuse circuit outputs output signals N1 and N2 to the individual output circuits, the signal levels of which are fixed to either H level or L level depending upon whether or not fuses f1 and f2 in the fuse circuit are disconnected. The output circuits are each provided with an output buffer circuit unit 112 and a pre-driver circuit unit 111 that drives the output buffer circuit unit. The driving capability of the pre-driver circuit unit is determined by the output signal from the fuse circuit.

Abstract: A first data store circuit is coupled to first and second voltage nodes of first and second voltage levels, respectively, and a control circuit outputs a transfer signal and a switching signal. A data transfer circuit is coupled between the first data store circuit and a second data store circuit and selectively transfers the data in the first data store circuit to the second data store circuit in response to the transfer signal. A first conductive line supplies the first voltage level to the second data store circuit and a second conductive line supplies the second voltage level to the second data store circuit. A first switch circuit is coupled between the second voltage node and the second conductive line and selectively connects the second voltage node to the second conductive line in response to the switching signal. Also a resistive element is coupled between the second conductive line and the first voltage node.