Abstract: A method of manufacturing a semiconductor memory device which includes forming a conductive layer for a floating gate above a semiconductor layer intervening a gate insulating film therebetween, then, forming, over the conductive layer, a first spacer comprising a first silicon oxide material and a second spacer adjacent with the first spacer and comprising a second silicon oxide material, the second silicon oxide material having an etching rate lower than that of the first silicon oxide material, selectively removing the conductive layer by using the first and the second spacers as a mask, and removing the first spacer to expose a portion of the conductive layer. Since the etching rate for the second spacer is lower compared with the etching rate for the first spacer, the etching amount of the second spacer caused upon removal of the first spacer can be suppressed and, as a result, the productivity and the reliability of the semiconductor memory device can be improved.

Abstract: A split gate nonvolatile memory cell is provided with a first diffusion region, a second diffusion region, and a channel region formed between the first and second diffusion regions, including a first channel region having a predetermined dopant concentration. The first channel region is positioned apart from the first and second diffusion regions.

Abstract: A non-volatile semiconductor memory device includes: a charge accumulation layer (CAL) on a substrate; a memory gate formed onto the substrate through the CAL; a first side gate formed through a first insulating film on a first side of the memory gate; a second side gate formed through a second insulating film on a second side opposite to the first side; a first impurity implantation region (IIR1) in the substrate adjacent the first side gate; a second impurity implantation region (IIR2) formed in the substrate on a side of the second side gate; and a channel region between IIR1 and IIR2. The channel region includes a first region corresponding to a boundary between the CAL and the substrate; a select side region between the first region and IIR1; and an assist side region between the first region and IIR2. The select side region is longer than the assist side region.

Abstract: A split gate nonvolatile memory cell is provided with a first diffusion region, a second diffusion region, and a channel region formed between the first and second diffusion regions, including a first channel region having a predetermined dopant concentration. The first channel region is positioned apart from the first and second diffusion regions.

Abstract: A non-volatile semiconductor memory device includes: a charge accumulation layer (CAL) on a substrate; a memory gate formed onto the substrate through the CAL; a first side gate formed through a first insulating film on a first side of the memory gate; a second side gate formed through a second insulating film on a second side opposite to the first side; a first impurity implantation region (IIR1) in the substrate adjacent the first side gate; a second impurity implantation region (IIR2) formed in the substrate on a side of the second side gate; and a channel region between IIR1 and IIR2. The channel region includes a first region corresponding to a boundary between the CAL and the substrate; a select side region between the first region and IIR1; and an assist side region between the first region and IIR2. The select side region is longer than the assist side region.

Abstract: A method of manufacturing a semiconductor memory device which includes forming a conductive layer for a floating gate above a semiconductor layer intervening a gate insulating film therebetween, then, forming, over the conductive layer, a first spacer comprising a first silicon oxide material and a second spacer adjacent with the first spacer and comprising a second silicon oxide material, the second silicon oxide material having an etching rate lower than that of the first silicon oxide material, selectively removing the conductive layer by using the first and the second spacers as a mask, and removing the first spacer to expose a portion of the conductive layer. Since the etching rate for the second spacer is lower compared with the etching rate for the first spacer, the etching amount of the second spacer caused upon removal of the first spacer can be suppressed and, as a result, the productivity and the reliability of the semiconductor memory device can be improved.

Abstract: A split gate nonvolatile memory cell is provided with a first diffusion region, a second diffusion region, and a channel region formed between the first and second diffusion regions, including a first channel region having a predetermined dopant concentration. The first channel region is positioned apart from the first and second diffusion regions.

Abstract: A first isolating trench with a predetermined depth is formed in a region where high voltage semiconductor elements are formed on a semiconductor substrate, and a portion of the walls of the first isolating trench is etched corresponding to a depth of a second isolating trench shallower than the first isolating trench to form a third isolating trench. An oxide film filled into the third isolating trench provides isolation between the high voltage semiconductor elements. Then, the second isolating trench is formed in a region where low voltage semiconductor elements are formed, and an oxide film filled into the second isolating trench is used to provide isolation between the low voltage semiconductor elements.

Abstract: For fabricating a semiconductor device having gate oxide films of different film thicknesses and a device isolation oxide film having an elevated device isolation characteristics, an oxidation-resistant film such as a nitride film is formed to cover the whole surface of a semiconductor substrate having a plurality of active regions defined by a device isolation oxide film and covered with a thin oxide film. The oxidation-resistant film and the thin oxide film are removed using, as a mask, a first resist exposing a first device formation area, and after the first resist is removed, a first gate oxide film is formed by thermally oxidizing the whole surface.

Abstract: A first isolating trench with a predetermined depth is formed in a region where high voltage semiconductor elements are formed on a semiconductor substrate, and a portion of the walls of the first isolating trench is etched corresponding to a depth of a second isolating trench shallower than the first isolating trench to form a third isolating trench. An oxide film filled into the third isolating trench provides isolation between the high voltage semiconductor elements. Then, the second isolating trench is formed in a region where low voltage semiconductor elements are formed, and an oxide film filled into the second isolating trench is used to provide isolation between the low voltage semiconductor elements.