Abstract: An imaging device includes a semiconductor substrate, a photoelectric conversion layer located above the semiconductor substrate, a first signal detection transistor that includes a first gate electrode above the semiconductor substrate and that outputs a signal corresponding to an electric potential of the first gate electrode, a second signal detection transistor that includes a second gate electrode above the semiconductor substrate and that outputs a signal corresponding to an electric potential of the second gate electrode, a first contact plug in contact with the first gate electrode, and a second contact plug in contact with the second gate electrode. The first gate electrode is electrically connected to the photoelectric conversion layer through the first contact plug. The second gate electrode and the second contact plug are electrically insulated from the photoelectric conversion layer.

Abstract: A switching circuit includes a first input terminal, an output terminal, and a first circuit that switches between outputting and not outputting, to the output terminal, a first voltage that is inputted to the first input terminal. The first circuit includes a first transistor and a second transistor that are connected in series between the first input terminal and the output terminal and a first voltage-dividing circuit that divides the first voltage and supplies the first voltage thus divided to a common node between the first transistor and the second transistor.

Abstract: A switching circuit includes a first input terminal, an output terminal, and a first circuit that switches between outputting and not outputting, to the output terminal, a first voltage that is inputted to the first input terminal. The first circuit includes a first transistor and a second transistor that are connected in series between the first input terminal and the output terminal and a first voltage-dividing circuit that divides the first voltage and supplies the first voltage thus divided to a common node between the first transistor and the second transistor.

Abstract: A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit.

Abstract: A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit.

Abstract: A differential output circuit includes: input transistors that receive differential input signals; n stages of cascode transistors (n?2) cascode connected to the input transistors; output terminals connected to the drains of n-th stage cascode transistors; an intermediate potential generating circuit that supplies an intermediate potential of potentials of the output terminals to the gates of the n-th stage cascode transistors; and a dividing circuit that supplies divided potentials resulting from the intermediate potential being divided into (n?1) stages to the respective gates of the (n?1)-th through first stages of the cascode transistors in descending order of potential.

Abstract: A differential output circuit includes: input transistors that receive differential input signals; n stages of cascode transistors (n?2) cascode connected to the input transistors; output terminals connected to the drains of n-th stage cascode transistors; an intermediate potential generating circuit that supplies an intermediate potential of potentials of the output terminals to the gates of the n-th stage cascode transistors; and a dividing circuit that supplies divided potentials resulting from the intermediate potential being divided into (n?1) stages to the respective gates of the (n?1)-th through first stages of the cascode transistors in descending order of potential.

Abstract: A storage section (101) stores a digital value. A compensation section (102) controls an offset value of an amplifier circuit (2) according to the digital value stored in the storage section (101). A determination section (103) determines whether the voltage value of an output signal (S2) from the amplifier circuit (2) is higher or lower than a reference voltage value. An adjustment section (104) adds a positive value to the digital value in the storage section (101) if the number of times the voltage value of the output signal is determined higher than the reference voltage value among k determination results by the determination section (103) is greater than the number of times the voltage value of the output signal is determined lower than the reference voltage value.

Abstract: An AD output average computation circuit 103 computes an average value of output values of 16 pixels from an AD converter 102. A subtractor 105 computes a difference value between the average value and a first AD output reference value. A clip circuit 106 selects analog offset correction or digital offset correction depending on the difference value. In the analog offset correction, a digital integrating circuit composed of a data hold circuit 108 and a subtractor 109 integrates the difference value to obtain an offset correction value, from which an offset correction voltage is generated by a DA converter 111 and an offset voltage generation circuit 112, to be used for correcting the offset of an amplifier 101. In the digital offset correction, a predetermined value is added to the output value of the AD converter 102 by an adder 113b to correct an offset amount.