Abstract: A semiconductor integrated circuit includes a plurality of logic circuits each being configurable to perform a logic function according to configuration data set therein, a memory that stores configuration information for use in setting the configuration data in each of the plurality of logic circuits, a test circuit configured to perform a test for detecting an error in each logic circuit, and an output circuit configured to output information indicating whether the error exists in one or more of the logic circuits based on a result of the test. In response to the output of the information indicating that the error exists, the configuration information stored in the memory is updated with new configuration information for setting the configuration data of each of the logic circuits other than one or more logic circuits having the error.

Abstract: A semiconductor integrated circuit includes a plurality of logic circuits each being configurable to perform a logic function according to configuration data set therein, a memory that stores configuration information for use in setting the configuration data in each of the plurality of logic circuits, a test circuit configured to perform a test for detecting an error in each logic circuit, and an output circuit configured to output information indicating whether the error exists in one or more of the logic circuits based on a result of the test. In response to the output of the information indicating that the error exists, the configuration information stored in the memory is updated with new configuration information for setting the configuration data of each of the logic circuits other than one or more logic circuits having the error.

Abstract: A microcomputer has a first external terminal for receiving an external control signal that indicates a test mode of peripheral circuits, and a second external terminal connected to a data bus. A CPU of the microcomputer provides a bus control signal in response to the external control signal passed through the first external terminal, to write data passed through the second external terminal into the peripheral circuits. Upon receiving the external control signal, a bus controller of the CPU stops a bus cycle requested by an execution controller of the CPU and starts a bus cycle requested by the external control signal, to test the peripheral circuits.

Abstract: The data processing apparatus which outputs information regarding the prefetching of an instruction in the destination of a branch instruction prior to the confirmation of its branch condition. The apparatus uses the output information to delete unexecuted memory access from a trace memory so as to accurately trace the execution sequence of the apparatus by an incircuit emulator. Bus attribute information is output which indicates that the bus cycle under operation is an instruction fetch bus cycle in the destination of a branch instruction. Additionally, status information regarding a prefetched instruction in the destination of a branch instruction is used in order to invalidate the prefetched instruction.

Abstract: A format converting circuit for numeric data comprises an operation unit which operates according to a mode decision signal to output an input data as it is or a two's complement of the input data; a storage device which stores a positive or negative sign data to be read out and is reset by an initializing signal to a positive data storing state; and a control circuit which operates in two conversion modes. One of the modes is a signed-to-unsigned conversion mode in which the control circuit controls the operation unit with the mode decision signal such that, if a sign bit of the input data is 0, the operation unit outputs the data as it is while, if the sign bit is 1, the operation unit outputs a two's complement of the input data. At the same time, the control circuit inverts the data stored in the storage device if the above-mentioned sign bit is 1.