Patents by Inventor Masami Jintyou

Masami Jintyou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113716
    Abstract: A semiconductor device including a miniaturized transistor is provided. The semiconductor device includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is provided over the first insulating layer and includes a second opening in a region overlapping with the first opening. The semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The second insulating layer is provided over the semiconductor layer. The third conductive layer is provided over the second insulating layer.
    Type: Application
    Filed: January 11, 2023
    Publication date: April 3, 2025
    Inventors: Yasuharu HOSAKA, Yukinori SHIMA, Masami JINTYOU, Masataka NAKADA, Junichi KOEZUKA, Kenichi OKAZAKI
  • Patent number: 12261119
    Abstract: A semiconductor device having favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The semiconductor layer includes an island-shaped top surface. The first insulating layer is provided in contact with a top surface and a side surface of the semiconductor layer. The first conductive layer is positioned over the first insulating layer and includes a portion overlapping with the semiconductor layer. In addition, the semiconductor layer includes a metal oxide, and the first insulating layer includes an oxide. The semiconductor layer includes a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer.
    Type: Grant
    Filed: September 21, 2023
    Date of Patent: March 25, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Toshimitsu Obonai, Masami Jintyou, Daisuke Kurosaki
  • Publication number: 20250098417
    Abstract: A semiconductor device includes first to third insulating layers and a transistor including a semiconductor layer, first to fourth conductive layers, and fourth to sixth insulating layers. The first conductive layer, the first insulating layer, the third conductive layer, the fifth insulating layer, the second insulating layer, the third insulating layer, and the second conductive layer overlap in this order. The first to third insulating layers and the second and third conductive layers include an opening reaching the first conductive layer. In the opening, the first insulating layer includes a protruding portion, and the fourth insulating layer is in contact with the top surface of the first insulating layer and side surfaces of the fifth insulating layer and the second insulating layer. The fifth insulating layer, an oxide of the third conductive layer, is in contact with top and side surfaces of the third conductive layer.
    Type: Application
    Filed: September 9, 2024
    Publication date: March 20, 2025
    Inventors: Masami JINTYOU, Daisuke KUROSAKI, Shiori TAMURA, Junichi KOEZUKA, Takahiro IGUCHI, Eiji SHIODA
  • Publication number: 20250098439
    Abstract: A display apparatus with high definition is provided. The display apparatus includes a transistor, a light-emitting device and a first insulating layer. The transistor includes a semiconductor layer, first to third conductive layers, and second and third insulating layers. The second insulating layer is provided over the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is provided over the second insulating layer and includes a second opening in a region overlapping with the first opening. The semiconductor layer is in contact with the top surface of the first conductive layer, the side surface of the second insulating layer, and the top surface and the side surface of the second conductive layer. The third insulating layer is provided over the semiconductor layer. The third conductive layer is provided over the third insulating layer. The first insulating layer is provided over the transistor.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 20, 2025
    Inventors: Yasuharu HOSAKA, Yukinori SHIMA, Masami JINTYOU, Masataka NAKADA, Junichi KOEZUKA, Kenichi OKAZAKI
  • Publication number: 20250081536
    Abstract: The transistor includes a first gate electrode, a first insulating film over the first gate electrode, an oxide semiconductor film over the first insulating film, a source electrode over the oxide semiconductor film, a drain electrode over the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, and a second gate electrode over the second insulating film. The first insulating film includes a first opening. A connection electrode electrically connected to the first gate electrode through the first opening is formed over the first insulating film. The second insulating film includes a second opening that reaches the connection electrode. The second gate electrode includes an oxide conductive film and a metal film over the oxide conductive film. The connection electrode and the second gate electrode are electrically connected to each other through the metal film.
    Type: Application
    Filed: November 15, 2024
    Publication date: March 6, 2025
    Inventors: Yoshiaki OIKAWA, Nobuharu OHSAWA, Masami JINTYOU, Yasutaka NAKAZAWA
  • Patent number: 12243447
    Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer. The third insulating layer is positioned over the semiconductor layer and includes a first opening over the semiconductor layer. The first conductive layer is positioned over the semiconductor layer, the first insulating layer is positioned between the first conductive layer and the semiconductor layer, and the second insulating layer is provided in a position that is in contact with a side surface of the first opening, the semiconductor layer, and the first insulating layer.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: March 4, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yukinori Shima, Masami Jintyou
  • Patent number: 12243943
    Abstract: A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: March 4, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiro Sato, Yasutaka Nakazawa, Takayuki Cho, Shunsuke Koshioka, Hajime Tokunaga, Masami Jintyou
  • Patent number: 12237389
    Abstract: A highly reliable semiconductor device with favorable electrical characteristics is provided. A semiconductor device includes a semiconductor layer, an insulating layer, a metal oxide layer, and a conductive layer. The semiconductor layer, the insulating layer, the metal oxide layer, and the conductive layer are stacked in this order. The semiconductor layer includes a first region, a pair of second regions, and a pair of third regions. The first region overlaps the metal oxide layer. The second regions sandwich the first region, overlap the insulating layer, and do not overlap the metal oxide layer. The third regions sandwich the first region and the pair of second regions, and do not overlap the insulating layer. The third region includes a portion having a lower resistance than the first region. The second region includes a portion having a higher resistance than the third region.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: February 25, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Masami Jintyou, Yukinori Shima
  • Publication number: 20250056837
    Abstract: A semiconductor device comprising an oxide semiconductor film, a gate electrode, a first insulating film, a source electrode, a drain electrode, and a second insulating film is provided. Each of a top surface of the gate electrode, a top surface of the source electrode, and a top surface of the drain electrode comprises a region in contact with the second insulating film. A top surface of the first insulating film comprises a region in contact with the gate electrode and a region in contact with the second insulating film and overlapping with the oxide semiconductor film in a cross-sectional view of the oxide semiconductor film. The oxide semiconductor film comprises a region in contact with the first insulating film and a region in contact with the second insulating film and adjacent to the region in contact with the first insulating film in the cross-sectional view.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Shunpei YAMAZAKI, Junichi KOEZUKA, Masami JINTYOU, Yukinori SHIMA, Takashi HAMOCHI, Yasutaka NAKAZAWA
  • Patent number: 12218144
    Abstract: The stability of a step of processing a wiring formed using copper, aluminum, gold, silver, molybdenum, or the like is increased. Moreover, the concentration of impurities in a semiconductor film is reduced. Moreover, the electrical characteristics of a semiconductor device are improved. In a transistor including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and a pair of conductive films being in contact with the oxide film and including copper, aluminum, gold, silver, molybdenum, or the like, the oxide film has a plurality of crystal parts and has c-axis alignment in the crystal parts, and the c-axes are aligned in a direction parallel to a normal vector of a top surface of the oxide semiconductor film or the oxide film.
    Type: Grant
    Filed: December 7, 2023
    Date of Patent: February 4, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Yasutaka Nakazawa, Yukinori Shima, Masami Jintyou, Masayuki Sakakura, Motoki Nakashima
  • Publication number: 20250040250
    Abstract: A semiconductor device including an oxide semiconductor in which on-state current is high is provided. The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. Furthermore, the first transistor and the second transistor are transistors having a top-gate structure. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. The first transistor provided in the driver circuit portion includes two gate electrodes between which the oxide semiconductor film is provided.
    Type: Application
    Filed: July 31, 2024
    Publication date: January 30, 2025
    Inventors: Junichi KOEZUKA, Masami JINTYOU, Yukinori SHIMA, Daisuke KUROSAKI, Masataka NAKADA, Shunpei YAMAZAKI
  • Patent number: 12199186
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided over the semiconductor layer. The first conductive layer is provided over the first insulating layer. The semiconductor layer includes a first region that overlaps with the first conductive layer and the first insulating layer, a second region that does not overlap with the first conductive layer and overlaps with the first insulating layer, and a third region that overlaps with neither the first conductive layer nor the first insulating layer. The semiconductor layer contains a metal oxide. The second region and the third region contain a first element. The first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium.
    Type: Grant
    Filed: October 11, 2023
    Date of Patent: January 14, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Okazaki, Masami Jintyou, Kensuke Yoshizumi
  • Publication number: 20240429170
    Abstract: A semiconductor device includes first to fourth conductive layers, first and second insulating layers, and a semiconductor layer. The first insulating layer is over the first conductive layer. The second conductive layer is over the first insulating layer. The second conductive layer and the first insulating layer include an opening reaching the first conductive layer. The semiconductor layer is in the opening. The second insulating layer is over the semiconductor layer. The third conductive layer is over the second insulating layer to fill the opening. The first insulating layer includes a depressed portion surrounding the opening in a plan view. The fourth conductive layer fills the depressed portion. Inside the opening, one side of the semiconductor layer faces the third conductive layer with the second insulating layer therebetween, and the other side of the semiconductor layer faces the fourth conductive layer with the first insulating layer therebetween.
    Type: Application
    Filed: May 20, 2024
    Publication date: December 26, 2024
    Inventors: Junichi KOEZUKA, Masami JINTYOU
  • Publication number: 20240421208
    Abstract: A transistor that can be miniaturized and highly reliable is provided. A semiconductor device includes a transistor and a first insulating layer. The transistor includes first to third conductive layers, a semiconductor layer, and a second insulating layer. The first insulating layer includes a first layer and a second layer over the first layer. The first insulating layer is over the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is over the second layer. The semiconductor layer is in contact with the first and second conductive layers and with a side surface of the first layer inside the first opening. The second insulating layer covers the semiconductor layer in the first opening, and the third conductive layer covers the second insulating layer in the first opening. The first insulating layer includes a second opening at a position different from the first opening.
    Type: Application
    Filed: June 10, 2024
    Publication date: December 19, 2024
    Inventors: Masami JINTYOU, Masayoshi DOBASHI, Junichi KOEZUKA
  • Patent number: 12170337
    Abstract: The transistor includes a first gate electrode, a first insulating film over the first gate electrode, an oxide semiconductor film over the first insulating film, a source electrode over the oxide semiconductor film, a drain electrode over the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, and a second gate electrode over the second insulating film. The first insulating film includes a first opening. A connection electrode electrically connected to the first gate electrode through the first opening is formed over the first insulating film. The second insulating film includes a second opening that reaches the connection electrode. The second gate electrode includes an oxide conductive film and a metal film over the oxide conductive film. The connection electrode and the second gate electrode are electrically connected to each other through the metal film.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: December 17, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Nobuharu Ohsawa, Masami Jintyou, Yasutaka Nakazawa
  • Publication number: 20240379856
    Abstract: The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films.
    Type: Application
    Filed: May 15, 2024
    Publication date: November 14, 2024
    Inventors: Shunpei YAMAZAKI, Masami JINTYOU, Yasutaka NAKAZAWA, Yukinori SHIMA
  • Patent number: 12142688
    Abstract: A semiconductor device comprising an oxide semiconductor film, a gate electrode, a first insulating film, a source electrode, a drain electrode, and a second insulating film is provided. Each of a top surface of the gate electrode, a top surface of the source electrode, and a top surface of the drain electrode comprises a region in contact with the second insulating film. A top surface of the first insulating film comprises a region in contact with the gate electrode and a region in contact with the second insulating film and overlapping with the oxide semiconductor film in a cross-sectional view of the oxide semiconductor film. The oxide semiconductor film comprises a region in contact with the first insulating film and a region in contact with the second insulating film and adjacent to the region in contact with the first insulating film in the cross-sectional view.
    Type: Grant
    Filed: August 31, 2023
    Date of Patent: November 12, 2024
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Yukinori Shima, Takashi Hamochi, Yasutaka Nakazawa
  • Publication number: 20240313122
    Abstract: The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween. The first region and the second region include a region having a higher carbon concentration than the third region.
    Type: Application
    Filed: March 21, 2024
    Publication date: September 19, 2024
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Patent number: 12087825
    Abstract: A metal oxide film includes indium, M, (M is Al, Ga, Y, or Sn), and zinc and includes a region where a peak having a diffraction intensity derived from a crystal structure is observed by X-ray diffraction in the direction perpendicular to the film surface. Moreover, a plurality of crystal parts is observed in a transmission electron microscope image in the direction perpendicular to the film surface. The proportion of a region other than the crystal parts is higher than or equal to 20% and lower than or equal to 60%.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: September 10, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuharu Hosaka, Toshimitsu Obonai, Yukinori Shima, Masami Jintyou, Daisuke Kurosaki, Takashi Hamochi, Junichi Koezuka, Kenichi Okazaki, Shunpei Yamazaki
  • Publication number: 20240272735
    Abstract: A touch panel including an oxide semiconductor film having conductivity is provided. The touch panel includes a transistor, a second insulating film, and a touch sensor. The transistor includes a gate electrode; a gate insulating film; a first oxide semiconductor film; a source electrode and a drain electrode; a first insulating film; and a second oxide semiconductor film. The second insulating film is over the second oxide semiconductor film so that the second oxide semiconductor film is positioned between the first insulating film and the second insulating film. The touch sensor includes a first electrode and a second electrode. One of the first and second electrodes includes the second oxide semiconductor film.
    Type: Application
    Filed: April 5, 2024
    Publication date: August 15, 2024
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Masami JINTYOU, Yasuharu HOSAKA, Naoto GOTO, Takahiro IGUCHI, Daisuke KUROSAKI, Junichi KOEZUKA