Patents by Inventor Masami Jintyou

Masami Jintyou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250261510
    Abstract: A semiconductor device that has both low power consumption and high performance is provided. The semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer. The second conductive layer is provided over the first insulating layer. The first insulating layer and the second conductive layer include an opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The second semiconductor layer is provided over the first semiconductor layer. The second insulating layer is provided over the second semiconductor layer. The third conductive layer is provided over the second insulating layer.
    Type: Application
    Filed: May 12, 2023
    Publication date: August 14, 2025
    Inventors: Masami JINTYOU, Yukinori SHIMA, Masakatsu OHNO, Junichi KOEZUKA
  • Publication number: 20250234591
    Abstract: A semiconductor device including a transistor having a minute size is provided.
    Type: Application
    Filed: April 7, 2023
    Publication date: July 17, 2025
    Inventors: Masami JINTYOU, Yukinori SHIMA, Junichi KOEZUKA, Takahiro IGUCHI
  • Publication number: 20250227957
    Abstract: A semiconductor device including a first conductive layer, a second conductive layer over the first conductive layer, a first insulating layer in contact with the first conductive layer and the second conductive layer, a third conductive layer over the first insulating layer, a semiconductor layer in contact with the third conductive layer, the first conductive layer, and the first insulating layer, a second insulating layer over the first insulating layer, the semiconductor layer, and the third conductive layer, and a fourth conductive layer over the second insulating layer is provided. A shortest distance from a top surface of the first conductive layer to a top surface of the second conductive layer is longer than a shortest distance from the top surface of the first conductive layer to a bottom surface of the fourth conductive layer.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 10, 2025
    Inventors: Yukinori SHIMA, Takahiro IGUCHI, Masakatsu OHNO, Masayoshi DOBASHI, Junichi KOEZUKA, Masami JINTYOU, Shunpei YAMAZAKI
  • Publication number: 20250221037
    Abstract: A semiconductor device (10) having a high degree of integration is provided. A first and a second transistors which are electrically connected to each other and a first insulating layer (110) are included. The first transistor (M2) includes a first semiconductor layer (108), a second insulating layer (106), and a first to a third conductive layers. The second transistor (M1) includes a second semiconductor layer (109), a third insulating layer (106), and a fourth to a sixth conductive layers. The first insulating layer is positioned over the first conductive layer (112a) and includes an opening reaching the first conductive layer. The second conductive layer (112b) is positioned over the first insulating layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and the second conductive layer. The third conductive layer (104) is positioned over the second insulating layer to overlap with the inner wall of the opening.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 3, 2025
    Inventors: Yasuharu HOSAKA, Takahiro IGUCHI, Chieko MISAWA, Ami SATO, Masayoshi DOBASHI, Masami JINTYOU
  • Publication number: 20250176270
    Abstract: The stability of a step of processing a wiring formed using copper, aluminum, gold, silver, molybdenum, or the like is increased. Moreover, the concentration of impurities in a semiconductor film is reduced. Moreover, the electrical characteristics of a semiconductor device are improved. In a transistor including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and a pair of conductive films being in contact with the oxide film and including copper, aluminum, gold, silver, molybdenum, or the like, the oxide film has a plurality of crystal parts and has c-axis alignment in the crystal parts, and the c-axes are aligned in a direction parallel to a normal vector of a top surface of the oxide semiconductor film or the oxide film.
    Type: Application
    Filed: December 30, 2024
    Publication date: May 29, 2025
    Inventors: Shunpei YAMAZAKI, Junichi KOEZUKA, Yasutaka NAKAZAWA, Yukinori SHIMA, Masami JINTYOU, Masayuki SAKAKURA, Motoki NAKASHIMA
  • Publication number: 20250169180
    Abstract: A semiconductor device having a high degree of integration is provided. The semiconductor device includes a first and a second transistor, and an insulating layer. The first transistor includes a source electrode, a drain electrode over the insulating layer over the source electrode, a first semiconductor layer in contact with a top surface of the source electrode, an inner wall of an opening provided in the insulating layer, and a top surface of the drain electrode, a first gate insulating layer in contact with a top surface and a side surface of the first semiconductor layer, and a first gate electrode over the first gate insulating layer that includes a region overlapping with the inner wall of the opening.
    Type: Application
    Filed: March 6, 2023
    Publication date: May 22, 2025
    Inventors: Yasuharu HOSAKA, Masami JINTYOU, Takahiro IGUCHI, Chieko MISAWA, Ami SATO, Masayoshi DOBASHI
  • Publication number: 20250169109
    Abstract: A highly reliable semiconductor device with favorable electrical characteristics is provided. A semiconductor device includes a semiconductor layer, an insulating layer, a metal oxide layer, and a conductive layer. The semiconductor layer, the insulating layer, the metal oxide layer, and the conductive layer are stacked in this order. The semiconductor layer includes a first region, a pair of second regions, and a pair of third regions. The first region overlaps the metal oxide layer. The second regions sandwich the first region, overlap the insulating layer, and do not overlap the metal oxide layer. The third regions sandwich the first region and the pair of second regions, and do not overlap the insulating layer. The third region includes a portion having a lower resistance than the first region. The second region includes a portion having a higher resistance than the third region.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Shunpei YAMAZAKI, Kenichi OKAZAKI, Masami JINTYOU, Yukinori SHIMA
  • Publication number: 20250169175
    Abstract: A novel semiconductor device is provided. The semiconductor device combines a lateral-channel transistor and a vertical-channel transistor. The lateral-channel transistor is employed as a p-channel transistor and the vertical-channel transistor is employed as an n-channel transistor to achieve a CMOS semiconductor device. An opening is provided in the insulating layer in a region overlapping with a gate electrode of the lateral-channel transistor, and the vertical-channel transistor is formed in the opening. An oxide semiconductor is used for a semiconductor layer of the vertical-channel transistor.
    Type: Application
    Filed: February 21, 2023
    Publication date: May 22, 2025
    Inventors: Yasuharu HOSAKA, Yukinori SHIMA, Masami JINTYOU, Masataka NAKADA, Junichi KOEZUKA, Kenichi OKAZAKI
  • Publication number: 20250159941
    Abstract: The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween. The first region and the second region include a region having a higher carbon concentration than the third region.
    Type: Application
    Filed: January 16, 2025
    Publication date: May 15, 2025
    Inventors: Shunpei YAMAZAKI, Junichi KOEZUKA, Masami JINTYOU, Yukinori SHIMA
  • Publication number: 20250160123
    Abstract: A semiconductor device including a transistor having a minute size is provided. The semiconductor device includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first semiconductor layer, a first conductive layer, a second conductive layer including a region overlapping with the first conductive layer with the first insulating layer therebetween, a third conductive layer, and a third insulating layer. The second conductive layer and the first insulating layer have a first opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface and a side surface of the second conductive layer, a side surface of the first insulating layer, and a top surface of the first conductive layer. The third insulating layer is provided over the first insulating layer, the first semiconductor layer, and the second conductive layer. The third conductive layer is provided over the third insulating layer.
    Type: Application
    Filed: March 6, 2023
    Publication date: May 15, 2025
    Inventors: Yasuharu HOSAKA, Yukinori SHIMA, Masami JINTYOU, Masataka NAKADA, Junichi KOEZUKA, Kenichi OKAZAKI
  • Publication number: 20250159936
    Abstract: A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.
    Type: Application
    Filed: January 8, 2025
    Publication date: May 15, 2025
    Inventors: Takahiro SATO, Yasutaka NAKAZAWA, Takayuki CHO, Shunsuke KOSHIOKA, Hajime TOKUNAGA, Masami JINTYOU
  • Publication number: 20250148942
    Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer. The third insulating layer is positioned over the semiconductor layer and includes a first opening over the semiconductor layer. The first conductive layer is positioned over the semiconductor layer, the first insulating layer is positioned between the first conductive layer and the semiconductor layer, and the second insulating layer is provided in a position that is in contact with a side surface of the first opening, the semiconductor layer, and the first insulating layer.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Yukinori SHIMA, Masami JINTYOU
  • Publication number: 20250151538
    Abstract: A semiconductor device including a miniaturized transistor is provided. The semiconductor device includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer. The first insulating layer has a first opening reaching the first conductive layer. The semiconductor layer is in contact with a top surface and a side surface of the first insulating layer and a top surface of the first conductive layer. The second conductive layer is provided over the semiconductor layer. The second conductive layer includes a second opening in a region overlapping with the first opening. The second insulating layer is provided over the semiconductor layer and the second conductive layer. The third conductive layer is provided over the second insulating layer.
    Type: Application
    Filed: February 6, 2023
    Publication date: May 8, 2025
    Inventors: Yasuharu HOSAKA, Yukinori SHIMA, Masami JINTYOU, Masataka NAKADA, Junichi KOEZUKA, Kenichi OKAZAKI
  • Publication number: 20250142887
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided over the semiconductor layer. The first conductive layer is provided over the first insulating layer. The semiconductor layer includes a first region that overlaps with the first conductive layer and the first insulating layer, a second region that does not overlap with the first conductive layer and overlaps with the first insulating layer, and a third region that overlaps with neither the first conductive layer nor the first insulating layer. The semiconductor layer contains a metal oxide. The second region and the third region contain a first element. The first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium.
    Type: Application
    Filed: December 26, 2024
    Publication date: May 1, 2025
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kenichi OKAZAKI, Masami JINTYOU, Kensuke YOSHIZUMI
  • Patent number: 12283634
    Abstract: The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween. The first region and the second region include a region having a higher carbon concentration than the third region.
    Type: Grant
    Filed: March 21, 2024
    Date of Patent: April 22, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Patent number: 12278292
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer containing a metal oxide, a first insulating layer, a second insulating layer, a third insulating layer containing a nitride, and a first conductive layer. The first insulating layer includes a projecting first region that overlaps with the semiconductor layer and a second region that does not overlap with the semiconductor layer and is thinner than the first region. The second insulating layer is provided to cover a top surface of the second region, a side surface of the first region, and the semiconductor layer. The first conductive layer is provided over the second insulating layer and a bottom surface of the first conductive layer over the second region includes a portion positioned below a bottom surface of the semiconductor layer.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: April 15, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Masami Jintyou, Takahiro Iguchi, Yukinori Shima
  • Publication number: 20250113716
    Abstract: A semiconductor device including a miniaturized transistor is provided. The semiconductor device includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is provided over the first insulating layer and includes a second opening in a region overlapping with the first opening. The semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The second insulating layer is provided over the semiconductor layer. The third conductive layer is provided over the second insulating layer.
    Type: Application
    Filed: January 11, 2023
    Publication date: April 3, 2025
    Inventors: Yasuharu HOSAKA, Yukinori SHIMA, Masami JINTYOU, Masataka NAKADA, Junichi KOEZUKA, Kenichi OKAZAKI
  • Patent number: 12261119
    Abstract: A semiconductor device having favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The semiconductor layer includes an island-shaped top surface. The first insulating layer is provided in contact with a top surface and a side surface of the semiconductor layer. The first conductive layer is positioned over the first insulating layer and includes a portion overlapping with the semiconductor layer. In addition, the semiconductor layer includes a metal oxide, and the first insulating layer includes an oxide. The semiconductor layer includes a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer.
    Type: Grant
    Filed: September 21, 2023
    Date of Patent: March 25, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Toshimitsu Obonai, Masami Jintyou, Daisuke Kurosaki
  • Publication number: 20250098439
    Abstract: A display apparatus with high definition is provided. The display apparatus includes a transistor, a light-emitting device and a first insulating layer. The transistor includes a semiconductor layer, first to third conductive layers, and second and third insulating layers. The second insulating layer is provided over the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is provided over the second insulating layer and includes a second opening in a region overlapping with the first opening. The semiconductor layer is in contact with the top surface of the first conductive layer, the side surface of the second insulating layer, and the top surface and the side surface of the second conductive layer. The third insulating layer is provided over the semiconductor layer. The third conductive layer is provided over the third insulating layer. The first insulating layer is provided over the transistor.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 20, 2025
    Inventors: Yasuharu HOSAKA, Yukinori SHIMA, Masami JINTYOU, Masataka NAKADA, Junichi KOEZUKA, Kenichi OKAZAKI
  • Publication number: 20250098417
    Abstract: A semiconductor device includes first to third insulating layers and a transistor including a semiconductor layer, first to fourth conductive layers, and fourth to sixth insulating layers. The first conductive layer, the first insulating layer, the third conductive layer, the fifth insulating layer, the second insulating layer, the third insulating layer, and the second conductive layer overlap in this order. The first to third insulating layers and the second and third conductive layers include an opening reaching the first conductive layer. In the opening, the first insulating layer includes a protruding portion, and the fourth insulating layer is in contact with the top surface of the first insulating layer and side surfaces of the fifth insulating layer and the second insulating layer. The fifth insulating layer, an oxide of the third conductive layer, is in contact with top and side surfaces of the third conductive layer.
    Type: Application
    Filed: September 9, 2024
    Publication date: March 20, 2025
    Inventors: Masami JINTYOU, Daisuke KUROSAKI, Shiori TAMURA, Junichi KOEZUKA, Takahiro IGUCHI, Eiji SHIODA