Abstract: When a first bus master device issues a bus request on a first request signal line, a centralized arbitration circuit in a system bus manage circuit issues a bus grant signal on a first grant signal line if the bus is available for use. This causes the first bus master device having gained the ownership of the bus to issue a read request to a first slave device. At this time a first signal line is designated. Even before the sending of the read data constituting a response to this read request to the first bus master device, a bus request from a second bus master device can be accepted if the data bus is unoccupied. Thus, the centralized arbitration circuit in the system bus manage circuit issues a grant signal on a second grant signal line. This causes the second bus master device having gained the ownership of the bus to designate a second end signal line, and to issue a read request to a second slave device.

Abstract: The present invention relates to information processing equipment having communication capabilities capable of executing a communication protocol processing at high speed and comprising a main processor and a communication processor. If a load factor of the main processor is higher than a predetermined threshold value, the main processor executes the communication protocol processing and if the load factor of the main processor is lower than the predetermined threshold value, the communication processor executes the communication protocol processing.