Patents by Inventor Masami Koketsu
Masami Koketsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120187520Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Inventors: Kunihiko KATO, Hideki YASUOKA, Masatoshi TAYA, Masami KOKETSU
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Patent number: 8169047Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.Type: GrantFiled: September 5, 2008Date of Patent: May 1, 2012Assignee: Renesas Electronics CorporationInventors: Kunihiko Kato, Hideki Yasuoka, Masatoshi Taya, Masami Koketsu
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Patent number: 8008788Abstract: A technique for positioning a semiconductor chip and a mounting substrate with high precision using an alignment mark. In a semiconductor chip, a mark is formed in an alignment mark formation region over a semiconductor substrate in the same layer as an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. Pattern P1a is formed in the same layer as a second layer wiring, pattern P1b is formed in the same layer as a first layer wiring, pattern P2 is formed in the same layer as a gate electrode, and pattern P3 is formed in the same layer as an element isolation region.Type: GrantFiled: February 4, 2009Date of Patent: August 30, 2011Assignee: Renesas Electronics CorporationInventors: Masami Koketsu, Toshiaki Sawada
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Publication number: 20110180877Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.Type: ApplicationFiled: April 6, 2011Publication date: July 28, 2011Inventors: Masami KOKETSU, Toshiaki Sawada
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Publication number: 20100244137Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.Type: ApplicationFiled: June 10, 2010Publication date: September 30, 2010Inventors: Keiichi YOSHIZUMI, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
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Patent number: 7759763Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.Type: GrantFiled: May 6, 2008Date of Patent: July 20, 2010Assignee: Renesas Technology Corp.Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
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Patent number: 7592669Abstract: With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p? type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p? type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.Type: GrantFiled: July 11, 2007Date of Patent: September 22, 2009Assignee: Renesas Technology Corp.Inventors: Hideki Yasuoka, Keiichi Yoshizumi, Masami Koketsu
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Publication number: 20090206411Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.Type: ApplicationFiled: February 4, 2009Publication date: August 20, 2009Inventors: Masami KOKETSU, Toshiaki Sawada
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Patent number: 7514749Abstract: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.Type: GrantFiled: May 18, 2008Date of Patent: April 7, 2009Assignee: Renesas Technology Corp.Inventors: Kunihiko Kato, Masami Koketsu, Shigeya Toyokawa, Keiichi Yoshizumi, Hideki Yasuoka, Yasuhiro Takeda
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Publication number: 20090065888Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a main surface of a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region in circular form, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.Type: ApplicationFiled: September 5, 2008Publication date: March 12, 2009Inventors: KUNIHIKO KATO, Hideki Yasuoka, Masatoshi Taya, Masami Koketsu
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Publication number: 20080258236Abstract: With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p? type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p? type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.Type: ApplicationFiled: July 11, 2007Publication date: October 23, 2008Inventors: Hideki Yasuoka, Keiichi Yoshizumi, Masami Koketsu
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Publication number: 20080220580Abstract: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.Type: ApplicationFiled: May 18, 2008Publication date: September 11, 2008Inventors: Kunihiko KATO, Masami KOKETSU, Shigeya TOYOKAWA, Keiichi YOSHIZUMI, Hideki YASUOKA, Yasuhiro TAKEDA
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Publication number: 20080211029Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.Type: ApplicationFiled: May 6, 2008Publication date: September 4, 2008Inventors: Keiichi YOSHIZUMI, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
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Patent number: 7393737Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.Type: GrantFiled: August 8, 2006Date of Patent: July 1, 2008Assignee: Renesas Technology Corp.Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
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Patent number: 7391083Abstract: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.Type: GrantFiled: April 18, 2006Date of Patent: June 24, 2008Assignee: Renesas Technology Corp.Inventors: Kunihiko Kato, Masami Koketsu, Shigeya Toyokawa, Keiichi Yoshizumi, Hideki Yasuoka, Yasuhiro Takeda
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Patent number: 7259054Abstract: With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p? type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p? type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.Type: GrantFiled: November 15, 2004Date of Patent: August 21, 2007Assignee: Renesas Technology Corp.Inventors: Hideki Yasuoka, Keiichi Yoshizumi, Masami Koketsu
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Publication number: 20070069326Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.Type: ApplicationFiled: August 8, 2006Publication date: March 29, 2007Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
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Publication number: 20060237795Abstract: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.Type: ApplicationFiled: April 18, 2006Publication date: October 26, 2006Inventors: Kunihiko Kato, Masami Koketsu, Shigeya Toyokawa, Keiichi Yoshizumi, Hideki Yasuoka, Yasuhiro Takeda
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Publication number: 20050104098Abstract: With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions aced away from p? type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p? type semiconductor regions (on the drain sides in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.Type: ApplicationFiled: November 15, 2004Publication date: May 19, 2005Inventors: Hideki Yasuoka, Keiichi Yoshizumi, Masami Koketsu