Abstract: A communication system for use with a network for transmitting fixed-length cells from a transmitting terminal via a virtual connection in the network to a receiving terminal.

Abstract: A first storage unit stores a reception count, which is the number of simultaneously-occurring messages for each of subscribers corresponding to subscriber identification information. A second storage unit stores a predetermined number of the simultaneously-occurring messages, which is an upper limit of allowing the messages to occur in parallel, for each of the subscribers corresponding to the subscriber identification information. A third storage unit stores each message identification information corresponding to each of the simultaneously-occurring messages, together with the order of occurrence, for each of the subscribers corresponding to the subscriber identification information. A control unit controls transfers of the simultaneously-occurring messages, by controlling the first, second, and third storage means according to the transfer order identification information, the subscriber identification information, and the message identification information extracted from the received data unit.

Abstract: A performance monitor system monitors a number of errors occurring in data processed in a communication apparatus having a duplex configuration formed of two systems. The performance monitor system includes a first unit for monitoring a number of errors occurring in data processed in one of the two systems a second unit for monitoring a number of errors occurring in data processed in another one of the two systems and a control unit for controlling operations of the first and second units. Each of the first and second units has a first counter outputting a first error count value and a second counter outputting a second error count value. The control unit controls the first and second counters so that the sum of the first and second error count values obtained in the first unit is equal to sum of those obtained in the second unit.

Abstract: In a data access device for writing into or read from a data conversion table on the basis of a clock signal extracted from a cell being transferred over a line, a clock signal generator of the invention generates a second clock signal which differs from the first clock signal extracted from an incoming cell. A write/read control unit writes data into or reads data for maintenance from the data conversion table on the basis of either the first clock signal or the second clock signal when the line is normal. In the event of the occurrence of a failure in the line, on the other hand, the write/read control circuit permits the data conversion table to be written into or read from for maintenance on the basis of the second clock signal.

Abstract: A communication system for transmitting a fixed-length cell converted from a variable-length information including data and a destination of the data. The system includes a cell assembly/disassembly device for performing bi-directional conversion between the variable-length information and the fixed-length cell, a routing control device for receiving the fixed-length cell converted from the variable-length information by the cell assembly/disassembly device, for analyzing the destination of the data and for controlling a routing of the fixed-length cell based on the analyzed destination, and having an error detecting device for detecting an error of the variable-length information in the fixed-length cell, and a network for connecting the cell assembly/disassembly device and the routing control device by a fixed capacity path and for connecting the routing control device to another routing control device by the fixed capacity path or a variable capacity path.

Abstract: A switch interface unit, a monitor unit, and a control system interface unit are connected as external units to a highway to which a subscriber information processing unit is also connected so that a monitoring process, that is, a special study process, can be simplified and a cost charged for the subscriber information processing unit can be prevented from increasing greatly. Furthermore, in an accounting process, accounting parameters are accumulated in an accounting information accumulating unit for variations on compressed source addresses, not on source addresses. As a result, the accounting information accumulating unit, etc. can be realized with normal circuit elements only.

Abstract: A self-routing exchange which includes switch modules connected in multiple stages. A synchronous transfer mode (STM) circuit switch module, which is capable of changing over a connection relationship between incoming highways and outgoing highways, is provided between the multistage-connected switch modules and self-routing switch modules. Asynchronous transfer mode (ATM) switch modules are provided as switch modules in preceding and succeeding stages of the circuit switching module. In dependence upon the number m of self-routing switch modules, a controller sets, by means of software, the connection relationship between the incoming and outgoing highways in each of space switches incorporated within the circuit switching module. As a result, the total mn-number of incoming highways from the self-routing switch modules are connected to respective ones of mn-number of outgoing highways set by the controller.

Abstract: A control data transmission system controls an electronic switching system with few signal lines. Control data are split into a plurality of fixed-length bit blocks. The control data sequence number specification signals identify the fixed-length bit blocks. The control data sequence number specification signals are paired with corresponding control data signals carrying the contents of one of the fixed-length bit blocks and a control data validity specification signal for validating transmission of the control data. The control data sequence number specification signals are decoded and the contents of respective bit blocks carried by the control data signals are stored according to the decoding result and the control data validity specification signal. When the contents of the fixed-length bit blocks carried by the control data signals for one unit of control data are stored, the control data are analyzed.

Abstract: An ATM (asynchronous transfer mode) exchange has a buffer for system #0 and a buffer for system #1 providing P-MEM's for storing data including an A bit and for a VCI/VPI currently in use is set to "1'. Upon detecting a switchover between the systems, every B bit is reset to "0". When the exchange while changing from a master to a slave receives a cell having a slave indication and while changing from a slave to a master it receives a cell having a master indication, respective systems rewrite B bits for VCI/VPI's of respective cells to "1". In the meantime, each of the P-MEM's calculates exclusive "OR" operations between the A bit and the B bit for every VCI/VPI, and further obtains a disjunction among all the exclusive "OR" operations thus obtained. Then, when both P-MEM's obtain "0" for their respective disjunctions, cells are read out from one of the buffers in the system changing from a slave to a master.

Abstract: A cell having an attribute of a point-to-multipoint connection is distributed to each of a number of subscribers using a point-to-multipoint connection distributing switch to be provided in parallel with a point-to-point connection, concentrating and distributing switch. Therefore, a hardware configuration can be simply established. Besides, both a point-to-point connection, and a point-to-multipoint connection can be made only by switching a cell to each switching unit, and a software configuration can thus be simplified.

Abstract: A supervision control system for an ATM cell switching system counts the number of cells transmitted from a subscriber in a predetermined duration unit, attaches a sign to the cells when the counted value exceeds a predetermined value, and discards the cells to which the sign is attached when a buffer does not have enough capacity during a cell multiplexation.

Abstract: An error check of a signaling data divided into divided signaling data transferred asynchronously in a unit of cells is performed in a signaling data receiving and processing unit in a digital exchange. The exchange is connected with terminal equipment arranged in a narrow band ISDN environment in a broadband ISDN system. The error check is performed by calculating an error check code for every byte of the signaling data as it is received, accumulating the result until the cyclic redundancy code, encountered in the last byte of the signaling data, is accumulated and performing matching between the accumulated result and a constant value produced based on the CRC system. The checking is performed while the signaling data is stored in a data memory in the signaling data receiving and processing unit.

Abstract: A first form of an ATM channel testing apparatus tests an ATM channel by having a test cell detector in each switch to detect whether or not the switch appropriately switches a test cell generated by a test cell generating trunk. A second form of an ATM channel testing apparatus easily tests an ATM channel by having test cell generators provided for the respective input highways sequentially generating test cells including test cell identifying information and input highway identifying information, and having test cell checkers provided respectively for the output highways simply tally the test cells by the respective input highways. A third form of an ATM channel testing apparatus tests an ATM channel with less pieces of hardware by having turnaround parts in respective ordinary trunks sequentially turn around a test cell generated by a test cell generating trunk to be finally returned to the test cell generating trunk.

Abstract: An apparatus for detecting a fault in an ATM switch includes a stored cell number detection unit which detects a number of cells stored in the FIFO memory. A difference detection unit detects a difference between the number of cells stored in the FIFO memory and a predicted number of cells which must be stored in the FIFO memory. A difference evaluation unit determines whether or not the switch element has a fault on the basis of the difference detected by the the difference detection unit.

Abstract: A main processor assigns originated-call processings to each of a plurality of call processors in the sequence of call originations according to the first principle of this invention. A switching state controller collects usage information about a plurality of buffers composing the switching network in the ATM exchanger. The call processors to which call processings are assigned perform the call processings based on the content of switching state controller a main processor assigns a call processing for an originated call to one of a plurality of call processors by referring to the call processing assignment table memory with the virtual channel identifier corresponding to an originated call according to the second principle of this invention thus, call processing loads are distributed among call processors.

Abstract: Recognizers are provided in respective self-routing modules in respective stages of a channel operating according to a multi-stage self-routing method. A recognizer sets a stage number to the switches in the self-routing module of the stage it belongs to by recognizing a stage number setting signal supplied from a self-routing module in the preceding stage. Updaters are provided in respective self-routing modules. An updater updates a stage number setting signal supplied from a self-routing module in the preceding stage and outputs it to a self-routing module in the succeeding stage. A stage number setter is provided in a virtual channel controller connected before a channel. It outputs predetermined stage number setting signals to a self-routing module in the first stage of a channel. Stage numbers specified by the stage number setting signals are autonomously set when the stage number setting signals sequentially pass through self-routing modules in respective stages.

Abstract: An index value output circuit outputs an index value in response to a VCI added to the first signaling cell outputted from a terminal unit. A switching data output circuit outputs switching data for determining a path for signaling cells, based on the index value. Hence, by revising the index value according to a congestion state of an ATM switch, the above path is dynamically changed. The same index value is inserted in the second and subsequent signaling cells outputted from the terminal unit. Because switching data are based on the same index value, all signaling cells from the same terminal units are fed to the same signaling terminator.

Abstract: An ATM switching system includes two ATM switches which are the same as each other. Each of the ATM switches includes a switch buffer, and a cell counter which indicates the number of cells in the switch buffer. Each of the ATM switches also includes a difference calculator, which calculates the difference between the number of cells in the two switch buffers when one of the ATM switches is changed from an out-of-service state to a slave mode. At this time, the other ATM switch operates in a master mode. Each of the ATM switches further includes a dummy cell generator, which generates a number of dummy cells which corresponds to the difference calculated by the difference calculator. The generated dummy cells are written into the switch buffer in the slave mode. When it is determined that when all of the dummy cells have been output from the switch buffer, the two ATM switches are syunchronized with each other.

Abstract: A digital switch module for a time division digital switching system includes an encoding law conversion memory and a control memory. The encoding law conversion memory has previously stored therein conversion data for converting between different types of encoding laws. For example, the A-law and .mu.-law encoding laws set forth in CCITT Recommendation G.711 can be converted by a digital switch module according to the present invention. The encoding law conversion memory includes a read only memory having regions for conversion between A-law and .mu.-law encoded data and for nonconversion of both A-law and .mu.-law encoded data. The control memory designates which of the regions in the encoding law conversion memory is to be used during each time slot, thus dynamically controlling whether data passing through the digital switch module is converted or not. The type of conversion or nonconversion designated by the control memory can be determined by the type of data, e.g.

Abstract: A supervision control system for an ATM cell switching system counts the number of cells transmitted from a subscriber in a predetermined duration unit, attaches a sign to the cells when the counted value exceeds a predetermined value, and discards the cells to which the sign is attached when a buffer does not have enough capacity during a cell multiplexation.