Patents by Inventor Masamichi Asano
Masamichi Asano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10910039Abstract: A semiconductor device constituting a decoder circuit for memory selection and having a smaller area is provided by using surrounding gate transistors (SGTs), which are vertical transistors. In a decoder circuit formed by a plurality of MOS transistors arranged in m rows and n columns, the MOS transistors that constitute the decoder circuit are arranged on a planar silicon layer formed on a substrate. Each has a structure including a drain, a gate, and a source arranged in a vertical direction, the gate surrounding a semiconductor pillar. The planar silicon layer is formed by a first active region of a first conductivity type and a second active region of a second conductivity type, and the regions are connected to each other via a conductive region formed on the surface of the planar silicon layer. Consequently, a semiconductor device that constitutes a decoder circuit having a smaller area is provided.Type: GrantFiled: April 17, 2019Date of Patent: February 2, 2021Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Masamichi Asano
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Publication number: 20190348109Abstract: A semiconductor device constituting a decoder circuit for memory selection and having a smaller area is provided by using surrounding gate transistors (SGTs), which are vertical transistors. In a decoder circuit formed by a plurality of MOS transistors arranged in m rows and n columns, the MOS transistors that constitute the decoder circuit are arranged on a planar silicon layer formed on a substrate. Each has a structure including a drain, a gate, and a source arranged in a vertical direction, the gate surrounding a semiconductor pillar. The planar silicon layer is formed by a first active region of a first conductivity type and a second active region of a second conductivity type, and the regions are connected to each other via a conductive region formed on the surface of the planar silicon layer. Consequently, a semiconductor device that constitutes a decoder circuit having a smaller area is provided.Type: ApplicationFiled: April 17, 2019Publication date: November 14, 2019Inventors: Fujio MASUOKA, Masamichi ASANO
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Patent number: 10311945Abstract: A semiconductor device constituting a decoder circuit for memory selection and having a smaller area is provided by using surrounding gate transistors (SGTs), which are vertical transistors. In a decoder circuit formed by a plurality of MOS transistors arranged in m rows and n columns, the MOS transistors that constitute the decoder circuit are arranged on a planar silicon layer formed on a substrate. Each has a structure including a drain, a gate, and a source arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer is formed by a first active region of a first conductivity type and a second active region of a second conductivity type, and the regions are connected to each other via a silicide layer formed on the surface of the planar silicon layer. Consequently, a semiconductor device that constitutes a decoder circuit having a smaller area is provided.Type: GrantFiled: October 19, 2015Date of Patent: June 4, 2019Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9876504Abstract: A semiconductor device includes a 3-input NAND decoder having six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.Type: GrantFiled: July 20, 2016Date of Patent: January 23, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9716092Abstract: A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit.Type: GrantFiled: October 27, 2016Date of Patent: July 25, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9646991Abstract: A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NOR circuit. The NOR circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NOR circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NOR circuit.Type: GrantFiled: November 4, 2015Date of Patent: May 9, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9641179Abstract: A semiconductor device includes a 3-input NOR decoder having six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.Type: GrantFiled: July 20, 2016Date of Patent: May 2, 2017Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9627496Abstract: A semiconductor device includes a two-input NOR circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NOR circuit having a small area.Type: GrantFiled: August 12, 2015Date of Patent: April 18, 2017Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9627407Abstract: A semiconductor device includes a 2-input NOR decoder and an inverter that have six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.Type: GrantFiled: July 20, 2016Date of Patent: April 18, 2017Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9601510Abstract: A semiconductor device has a small area and constitutes a CMOS 3-input NAND circuit by using surrounding gate transistors (SGTs) that are vertical transistors. In a 3-input NAND circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NAND circuit have the following configuration. Planar silicon layers are disposed on a substrate. The drain, gate, and source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planer silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NAND circuit with a small area is provided.Type: GrantFiled: September 16, 2015Date of Patent: March 21, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9590631Abstract: A semiconductor device includes a 2-input NAND decoder and an inverter that have six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.Type: GrantFiled: July 20, 2016Date of Patent: March 7, 2017Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Masamichi Asano
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Publication number: 20170047328Abstract: A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit.Type: ApplicationFiled: October 27, 2016Publication date: February 16, 2017Inventors: FUJIO MASUOKA, MASAMICHI ASANO
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Publication number: 20160344389Abstract: A semiconductor device includes a 2-input NAND decoder and an inverter that have six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.Type: ApplicationFiled: July 20, 2016Publication date: November 24, 2016Inventors: Fujio MASUOKA, Masamichi ASANO
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Publication number: 20160329348Abstract: A semiconductor device includes a 2-input NOR decoder and an inverter that have six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Inventors: Fujio MASUOKA, Masamichi ASANO
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Publication number: 20160329898Abstract: A semiconductor device includes a 3-input NOR decoder having six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Inventors: Fujio MASUOKA, Masamichi ASANO
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Publication number: 20160329899Abstract: A semiconductor device includes a 3-input NAND decoder having six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Inventors: Fujio MASUOKA, Masamichi ASANO
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Patent number: 9484424Abstract: A semiconductor device includes a two-input NAND circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NAND circuit having a small area.Type: GrantFiled: August 12, 2015Date of Patent: November 1, 2016Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9449988Abstract: A semiconductor device has a small area and constitutes a CMOS 3-input NOR circuit by using surrounding gate transistors (SGTs) which are vertical transistors. In the 3-input NOR circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NOR circuit have the following configuration: Planar silicon layers are disposed on a substrate. The drain, the gate, and the source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planar silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NOR circuit with a small area is provided.Type: GrantFiled: September 16, 2015Date of Patent: September 20, 2016Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Masamichi Asano
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Publication number: 20160056173Abstract: A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit.Type: ApplicationFiled: November 4, 2015Publication date: February 25, 2016Inventors: FUJIO MASUOKA, MASAMICHI ASANO
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Publication number: 20160056174Abstract: A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NOR circuit. The NOR circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NOR circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NOR circuit.Type: ApplicationFiled: November 4, 2015Publication date: February 25, 2016Inventors: FUJIO MASUOKA, MASAMICHI ASANO