Abstract: Disclosed is a semiconductor device including a semiconductor device including a substrate, a nitride semiconductor layer formed over the substrate and including an active region and an element isolation region, inert atoms being introduced into the element isolation region, a source electrode formed over the nitride semiconductor layer in the active region, a gate electrode formed over the nitride semiconductor layer in the active region away from the source electrode, and a drain electrode formed over the nitride semiconductor layer in the active region away from the gate electrode, the drain electrode including an end portion provided away from a boundary between the element isolation region and the active region by a first distance, wherein the first distance is greater than a second distance, the second distance being a distance where a concentration of the inert atoms diffused from the element isolation region into the active region becomes a first concentration, and an electron density in the active re

Abstract: In a semiconductor device including a multilayer pad, the multilayer pad comprises a first pad layer provided over a semiconductor substrate to have a first copper wiring region and a first intralayer insulating region provided within the first copper wiring region, and a second pad layer provided over the first pad layer via an interlayer insulating film to have a second copper wiring region and a second intralayer insulating region provided within the second copper wiring region. In the semiconductor device, the first copper wiring region, the first intralayer insulating region, the second copper wiring region, and the second intralayer insulating region are provided in the first and second pad layers such that the multilayer pad has a layout in which all the regions are covered with the copper wiring when the multilayer pad is perspectively viewed from a perpendicularly upper direction for the semiconductor substrate.

Abstract: A timing analysis method evaluates a performance of a target circuit that is to be designed, and includes calculating a correlation coefficient r between two arbitrary macro cells that are coupled and form the target circuit based on layout information including an arrangement of macro cells forming the target circuit and correlation information indicating a correlation between two macro cells that are coupled for each of arrangements of macro cell pairs, calculating a distribution function ? of a standard deviation of delay times of the two arbitrary macro cells based on the correlation coefficient ?, and carrying out a statistical timing analysis of the target circuit based on the correlation coefficient r and the distribution function ? of the standard deviation with respect to each of the macro cell pairs forming the target circuit.

Abstract: A timing analysis method evaluates a performance of a target circuit that is to be designed, and includes calculating a correlation coefficient r between two arbitrary macro cells that are coupled and form the target circuit based on layout information including an arrangement of macro cells forming the target circuit and correlation information indicating a correlation between two macro cells that are coupled for each of arrangements of macro cell pairs, calculating a distribution function ? of a standard deviation of delay times of the two arbitrary macro cells based on the correlation coefficient ?, and carrying out a statistical timing analysis of the target circuit based on the correlation coefficient r and the distribution function ? of the standard deviation with respect to each of the macro cell pairs forming the target circuit.

Abstract: In a semiconductor device including a multilayer pad, the multilayer pad comprises a first pad layer provided over a semiconductor substrate to have a first copper wiring region and a first intralayer insulating region provided within the first copper wiring region, and a second pad layer provided over the first pad layer via an interlayer insulating film to have a second copper wiring region and a second intralayer insulating region provided within the second copper wiring region. In the semiconductor device, the first copper wiring region, the first intralayer insulating region, the second copper wiring region, and the second intralayer insulating region are provided in the first and second pad layers such that the multilayer pad has a layout in which all the regions are covered with the copper wiring when the multilayer pad is perspectively viewed from a perpendicularly upper direction for the semiconductor substrate.

Abstract: A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.