Patents by Inventor Masamichi Matsuoka

Masamichi Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200238277
    Abstract: To provide a microchannel chip which is a chip provided internally with an inner space that can be used as a flow channel, and which is excellent in drug non-absorption properties of the channel. The microchannel chip has formed therein a plurality of openings H1, H2 and an inner space S connecting the plurality of openings H1, H2, and at least a part of the surface in contact with the inner space S is made of a fluorinated copolymer containing from 5 to 99 mol % of units based on CF2?CFX (X is a fluorine atom, a chlorine atom or CF3).
    Type: Application
    Filed: March 4, 2020
    Publication date: July 30, 2020
    Applicant: AGC Inc.
    Inventors: Masahiro OHKURA, Daisuke TAGUCHI, Masamichi IDE, Naoki MATSUOKA
  • Publication number: 20130203187
    Abstract: The semiconductor device of this invention includes a semiconductor substrate having a main surface, and a magnetoresistive element located over the main surface of the semiconductor substrate. Further, it includes a protective layer, a wiring, a first upper electrode, and a second upper electrode. The protective layer is disposed so as to cover the side surface of the magnetoresistive element. The wiring is located over the top of the magnetoresistive element. The first upper electrode substantially the same in dimensions in plan view as the magnetoresistive element is disposed over the magnetoresistive element. The second upper electrode is electrically coupled with the first upper electrode over the first upper electrode, and larger in dimensions in plan view than the first upper electrode.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 8, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masamichi MATSUOKA, Tatsuya FUKUMURA
  • Patent number: 8338817
    Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: December 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiro Moniwa, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida
  • Patent number: 8264023
    Abstract: A semiconductor device includes a semiconductor substrate, a lower electrode, a magnetoresistive element, an upper electrode, and a protective film. The lower electrode is formed over the semiconductor substrate. The magnetoresistive element includes a fixed layer, a tunneling insulating film, and a free layer. The upper electrode is disposed over the free layer. The protective film covers the sides intersecting the main surfaces of the lower electrode, the fixed layer, the tunneling insulating film, the free layer, and the upper electrode. The fixed layer, whose magnetization direction is fixed, is disposed over the lower electrode. The tunneling insulating film is disposed over the fixed layer. The free layer, whose magnetization direction is variable, is disposed over a main surface of the tunneling insulating film. The width of the upper electrode is smaller than that of each of the lower electrode and the fixed layer.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: September 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yosuke Takeuchi, Masamichi Matsuoka, Ryoji Matsuda, Keisuke Tsukamoto
  • Publication number: 20120068282
    Abstract: To provide a semiconductor device capable of suppressing a short circuit between an upper conductive element and a lower conductive element which constitute an MRAM, and a manufacturing method of the same. There are provided a semiconductor substrate having a main surface, a magnetic tunnel junction structure located over the main surface of the semiconductor substrate and including a pin layer, a tunnel insulating layer, and a free layer, a lower insulating layer contacting a lower side surface of the magnetic tunnel junction structure, a sidewall insulating layer located over the lower insulating layer in contact with the upper side surface of the magnetic tunnel junction structure, and exposing the top surface of the magnetic tunnel junction structure, and a conductive layer contacting the top surface of the magnetic tunnel junction structure exposed from the sidewall insulating layer.
    Type: Application
    Filed: July 22, 2011
    Publication date: March 22, 2012
    Inventors: Masamichi MATSUOKA, Tatsuya Fukumura, Fumihiko Nitta
  • Publication number: 20120037874
    Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.
    Type: Application
    Filed: October 21, 2011
    Publication date: February 16, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Masahiro MONIWA, Fumihiko NITTA, Masamichi MATSUOKA, Satoshi IIDA
  • Patent number: 8071456
    Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: December 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiro Moniwa, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida
  • Publication number: 20110198715
    Abstract: The semiconductor device of this invention includes a semiconductor substrate having a main surface, and a magnetoresistive element located over the main surface of the semiconductor substrate. Further, it includes a protective layer, a wiring, a first upper electrode, and a second upper electrode. The protective layer is disposed so as to cover the side surface of the magnetoresistive element. The wiring is located over the top of the magnetoresistive element. The first upper electrode substantially the same in dimensions in plan view as the magnetoresistive element is disposed over the magnetoresistive element. The second upper electrode is electrically coupled with the first upper electrode over the first upper electrode, and larger in dimensions in plan view than the first upper electrode.
    Type: Application
    Filed: February 8, 2011
    Publication date: August 18, 2011
    Inventors: Masamichi MATSUOKA, Tatsuya Fukumura
  • Publication number: 20110156181
    Abstract: A semiconductor device is provided which can further suppress the leakage of a magnetic field in a magnetoresistive element, and which can further improve the performance of the semiconductor device. A semiconductor device includes a semiconductor substrate, a lower electrode, a magnetoresistive element, an upper electrode, and a protective film. The lower electrode is formed over a main surface of the semiconductor substrate. The magnetoresistive element includes a fixed layer, a tunneling insulating film, and a free layer. The upper electrode is disposed over the other main surface opposite to one main surface of the free layer opposed to the tunneling insulating film. The protective film covers the sides intersecting the main surfaces of the lower electrode, the fixed layer, the tunneling insulating film, the free layer, and the upper electrode.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 30, 2011
    Inventors: Yosuke TAKEUCHI, Masamichi MATSUOKA, Ryoji MATSUDA, Keisuke TSUKAMOTO
  • Publication number: 20110156182
    Abstract: To provide a semiconductor device capable of further suppressing the leakage of magnetic field in a magnetoresistive element and capable of further improving performance. There is provided a semiconductor device comprising a semiconductor substrate, a magnetoresistive element, a wire, barrier layers, and cladding layers. The semiconductor substrate has a main surface. The magnetoresistive element is located over the main surface of the semiconductor substrate. The wire is located over the magnetoresistive element. The barrier layers are arranged so as to continuously cover the side surface and the top surface of the wire. The cladding layers are arranged so as to continuously cover the surfaces of the barrier layers facing the wire and the surfaces on the opposite side. A plurality of memory units including the magnetoresistive element, the wire, the barrier layers, and the cladding layers is formed.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 30, 2011
    Inventors: Yosuke TAKEUCHI, Masamichi Matsuoka, Ryoji Matsuda
  • Patent number: 7902539
    Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: March 8, 2011
    Assignee: Renesas Technology Corp.
    Inventors: Masahiro Moniwa, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida
  • Publication number: 20100323491
    Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.
    Type: Application
    Filed: August 27, 2010
    Publication date: December 23, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Masahiro MONIWA, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida
  • Publication number: 20090140234
    Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.
    Type: Application
    Filed: November 20, 2008
    Publication date: June 4, 2009
    Inventors: Masahiro Moniwa, Fumihiko Nitta, Masamichi Matsuoka, Satoshi Iida
  • Publication number: 20070164342
    Abstract: A polysilicon film forming a memory gate interconnection and the like includes a part extending from a part positioned on one side surface of a control gate interconnection to a side opposite to a side where the control gate interconnection is positioned, and that part serves as a pad portion. A contact hole is formed to expose the pad portion. The height of a part of the polysilicon film that is positioned on one side surface of the control gate interconnection is set equal to or lower than the height of the control gate interconnection so that the polysilicon film forming a memory gate interconnection and the like does not two-dimensionally overlap the control gate interconnection. Therefore, a semiconductor memory device with increased process margin can be obtained.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 19, 2007
    Inventors: Tsutomu Okazaki, Motoi Ashida, Hiroji Ozaki, Tsuyoshi Koga, Daisuke Okada, Masamichi Matsuoka
  • Patent number: 7113454
    Abstract: A disc player for playing back a disc that includes a plurality of folders, each folder including music files, includes a folder specifying unit for selecting a folder playback mode and specifying one folder and a playback unit for reading the music files in the specified folder from the disc to sequentially play back the read music files in the folder playback mode. The playback unit reads and plays back the music files from the disc in an order determined by a playback order determining unit in a folder random playback mode. The playback unit repeatedly plays back at least one music file in the specified folder in a folder repeat playback mode. The playback unit scans and plays back the first few seconds of each music file in the folder in a folder scan playback mode.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: September 26, 2006
    Assignee: Alpine Electronics, Inc.
    Inventor: Masamichi Matsuoka
  • Patent number: 7113456
    Abstract: A method and apparatus for reading multisession discs in which both standard CD-DA format and compressed music formats, such as MP3, may be utilized on the same disc. High speed reading of data into shock proof memory, analysis of available memory and storage of analyzed record structures are used to provide playback of music in both formats and, if desired, in a random playback order.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: September 26, 2006
    Assignee: Alpine Electronics, Inc.
    Inventors: Manabu Kusano, Shinji Wakabayashi, Masamichi Matsuoka
  • Publication number: 20050230716
    Abstract: The object of the present invention is to suppress the increase of the contact resistance at the interface between the metal layer and the silicon plug in the wiring structure in which a metal layer is formed on and connected to a silicon plug. For its achievement, a lower semiconductor layer (drain) of a vertical-type MISFET is connected to an intermediate metal layer via an underlying plug composed of a polycrystalline silicon film, and a trap layer composed of a silicon nitride (TiN) film is formed on a part of the surface of the intermediate metal layer so as to surround the plug. The trap layer is formed in order to prevent an undesired high-resistance oxide layer from being formed at the interface between the plug and the intermediate metal layer.
    Type: Application
    Filed: April 18, 2005
    Publication date: October 20, 2005
    Inventors: Satoshi Moriya, Toshiyuki Kikuchi, Akihiko Konno, Hidenori Sato, Naoki Yamamoto, Masamichi Matsuoka, Hiraku Chakihara, Akio Nishida
  • Publication number: 20040032800
    Abstract: A disc player for playing back a disc that includes a plurality of folders, each folder including music files, includes a folder specifying unit for selecting a folder playback mode and specifying one folder and a playback unit for reading the music files in the specified folder from the disc to sequentially play back the read music files in the folder playback mode. The playback unit reads and plays back the music files from the disc in an order determined by a playback order determining unit in a folder random playback mode. The playback unit repeatedly plays back at least one music file in the specified folder in a folder repeat playback mode. The playback unit scans and plays back the first few seconds of each music file in the folder in a folder scan playback mode.
    Type: Application
    Filed: March 21, 2003
    Publication date: February 19, 2004
    Inventor: Masamichi Matsuoka
  • Publication number: 20040032771
    Abstract: A method and apparatus for reading multisession discs in which both standard CD-DA format and compressed music formats, such as MP3, may be utilized on the same disc. High speed reading of data into shock proof memory, analysis of available memory and storage of analyzed record structures are used to provide playback of music in both formats and, if desired, in a random playback order.
    Type: Application
    Filed: March 17, 2003
    Publication date: February 19, 2004
    Inventors: Manabu Kusano, Shinji Wakabayashi, Masamichi Matsuoka
  • Patent number: 6576509
    Abstract: In forming a plug 21 of a polycrystalline silicon film in a contact hole 19 to which a bit line BL is connected, the upper surface of the plug 21 is retracted downward from the upper edge of the contact hole 19, and a plug 22 of a laminate of a TiN film 26 and a W film 27 is formed on the plug 21. Then, the W film deposited on the contact hole 19 is patterned to form a bit line BL having a width narrower than the diameter of the contact hole 19. Here, the W film 27 constituting part of the plug 22 in the contact hole 19 is etched, but the TiN film 26 constituting another part of the plug 22 is not almost etched.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: June 10, 2003
    Assignees: Hitachi Ltd., Hitachi ULSI Engineering Systems Co., Ltd.
    Inventors: Shigeya Toyokawa, Takashi Hashimoto, Kenichi Kuroda, Shoji Yoshida, Toshiyuki Iwaki, Masamichi Matsuoka