Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.

Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.

Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.

Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.

Abstract: In a bipolar transistor, an SIC layer is provided right under a genuine base region in order to suppress the Kirk effect and improve fT characteristic by thinning the film of the genuine base region. The higher the concentration of impurities in the SIC layer, the bigger the effect. When the impurity concentration of the SIC layer is high, the VCEO deteriorates so that the fT characteristic improvement and the Kirk effect suppression are in a trade off relationship with the VCEO. A second SIC layer is provided right under the genuine base region and in contact therewith, and a first SIC layer with a higher impurity concentration than the second SIC layer is formed right under the second SIC layer. The first SIC layer narrows the collector width and suppresses the Kirk effect whereas, the second SIC layer makes it possible to improve fT characteristic by cutting a lower edge of the genuine base region.