Patents by Inventor Masamichi Yanagida
Masamichi Yanagida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147857Abstract: A thermoelectric power generation system 20 includes a heat exchanger 1 having double tubes which are an inner tube 1a and an outer tube 1b, and a thermoelectric power generation module 2 mounted between the inner tube and the outer tube. The thermoelectric power generation module generates thermoelectric power using a temperature difference between a medium inside the inner tube and a medium outside the outer tube, and a highly thermal conductive elastic sheet 3a, 3b is mounted between the thermoelectric power generation module and the inner tube and/or the outer tube in close contact therewith.Type: ApplicationFiled: February 26, 2021Publication date: May 2, 2024Applicants: E-ThermoGentek Co., Ltd., KAWASAKI JUKOGYO KABUSHIKI KAISHA, KAWASAKI THERMAL ENGINEERING CO., LTD.Inventors: Takashi UNO, Nao MAJIMA, Michio OKAJIMA, Keiichi OHATA, Shutaro NAMBU, Makoto GODA, Minoru NAKAYASU, Yoma KANEDA, Masamichi SAKAGUCHI, Takahide YANAGIDA, Yusei MAEDA
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Patent number: 10490659Abstract: The present invention provides a semiconductor device that can achieve miniaturization or thinning of the size of the package while maintaining the characteristic of the MOSFET and reducing the on-resistance value, and a portable apparatus using the same. The gate electrodes 26 and 28 of the semiconductor chip 10 are disposed in the vicinity of the two side surfaces of the longitudinal direction (the x axis direction on the page) of the package 2, and the gate terminal 13 and 14 that is mounted with the gate electrodes 26 and 28 in a flip-chip manner are extended in the longitudinal direction of the package 2 and are derived to the outside from the two side surfaces 2A and 2B. Based on the configuration, it is capable of maximizing the size of the semiconductor chip with respect to the size of the package, and it is able to realize the high performance of the element characteristic for the module.Type: GrantFiled: December 27, 2016Date of Patent: November 26, 2019Assignee: UPI SEMICONDUCTOR CORP.Inventors: Masamichi Yanagida, Masashi Koyano, Nobuyoshi Matsuura, Hiroki Arai
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Patent number: 10438832Abstract: A semiconductor device manufacturing method is disclosed. The semiconductor device manufacturing method includes: a preparation step of preparing a semiconductor wafer; a removal step of removing a thickness part of the semiconductor wafer; and a cutting step of cutting the semiconductor wafer. In the removal step, a rib-shaped portion partially raised on a second main surface of the semiconductor wafer is used as an alignment mark, so that a cutter can align with the semiconductor wafer.Type: GrantFiled: April 12, 2018Date of Patent: October 8, 2019Assignee: uPI SEMICONDUCTOR CORP.Inventors: Masamichi Yanagida, Nobuyoshi Matsuura
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Publication number: 20180301366Abstract: A semiconductor device manufacturing method is disclosed. The semiconductor device manufacturing method includes: a preparation step of preparing a semiconductor wafer; a removal step of removing a thickness part of the semiconductor wafer; and a cutting step of cutting the semiconductor wafer. In the removal step, a rib-shaped portion partially raised on a second main surface of the semiconductor wafer is used as an alignment mark, so that a cutter can align with the semiconductor wafer.Type: ApplicationFiled: April 12, 2018Publication date: October 18, 2018Inventors: Masamichi Yanagida, Nobuyoshi Matsuura
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Publication number: 20170194294Abstract: The present invention provides a semiconductor device that can achieve miniaturization or thinning of the size of the package while maintaining the characteristic of the MOSFET and reducing the on-resistance value, and a portable apparatus using the same. The gate electrodes 26 and 28 of the semiconductor chip 10 are disposed in the vicinity of the two side surfaces of the longitudinal direction (the x axis direction on the page) of the package 2, and the gate terminal 13 and 14 that is mounted with the gate electrodes 26 and 28 in a flip-chip manner are extended in the longitudinal direction of the package 2 and are derived to the outside from the two side surfaces 2A and 2B. Based on the configuration, it is capable of maximizing the size of the semiconductor chip with respect to the size of the package, and it is able to realize the high performance of the element characteristic for the module.Type: ApplicationFiled: December 27, 2016Publication date: July 6, 2017Inventors: Masamichi Yanagida, Masashi Koyano, Nobuyoshi Matsuura, Hiroki Arai
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Patent number: 8018031Abstract: The invention realizes low on-resistance and high current flow in a semiconductor device in which a current flows in a thickness direction of a semiconductor substrate. A first MOS transistor having first gate electrodes and first source layers is formed on a front surface of a semiconductor substrate, and a second MOS transistor having second gate electrodes and second source layers is formed on a back surface thereof. A drain electrode connected to the semiconductor substrate, a first source electrode connected to the first source layers, a second source electrode connected to the second source layers, and a first penetration hole penetrating the semiconductor substrate are further formed. A first wiring connecting the first source electrode and the second source electrode is formed in the first penetration hole. The semiconductor substrate serves as a common drain region of the first and second MOS transistors.Type: GrantFiled: May 28, 2008Date of Patent: September 13, 2011Assignees: Semiconductor Components Industries, LLC, SANYO Semiconductor Co., Ltd.Inventor: Masamichi Yanagida
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Publication number: 20080296675Abstract: The invention realizes low on-resistance and high current flow in a semiconductor device in which a current flows in a thickness direction of a semiconductor substrate. A first MOS transistor having first gate electrodes and first source layers is formed on a front surface of a semiconductor substrate, and a second MOS transistor having second gate electrodes and second source layers is formed on a back surface thereof. A drain electrode connected to the semiconductor substrate, a first source electrode connected to the first source layers, a second source electrode connected to the second source layers, and a first penetration hole penetrating the semiconductor substrate are further formed. A first wiring connecting the first source electrode and the second source electrode is formed in the first penetration hole. The semiconductor substrate serves as a common drain region of the first and second MOS transistors.Type: ApplicationFiled: May 28, 2008Publication date: December 4, 2008Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventor: Masamichi YANAGIDA
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Patent number: 7413954Abstract: A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.Type: GrantFiled: September 21, 2005Date of Patent: August 19, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Hirotoshi Kubo, Junichiro Tojo, Hiroaki Saito, Masahito Onda, Satoshi Iwata, Masamichi Yanagida
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Publication number: 20070215938Abstract: Thinning a semiconductor substrate has been needed for reducing on-resistance in a semiconductor device such as a vertical MOS transistor, IGBT, or the like where a high current flows in the semiconductor substrate in a vertical direction. In this case, the thinning is performed to the extent that the semiconductor substrate does not warp with a heat treatment, so that there is a limitation in reduction of on-resistance. In the invention, openings such as trench holes are formed on a back surface side of a semiconductor substrate. Then, a drain electrode is formed being electrically connected with bottoms of these openings. In this case, a current path is formed short corresponding to the depths of the openings, thereby easily achieving low on-resistance.Type: ApplicationFiled: March 15, 2007Publication date: September 20, 2007Applicants: SANYO ELECTRIC CO., LTD., Sanyo Semiconductor Co., Ltd.Inventors: Masamichi Yanagida, Koujiro Kameyama, Kikuo Okada
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Publication number: 20070166905Abstract: In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.Type: ApplicationFiled: February 22, 2007Publication date: July 19, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Masamichi Yanagida, Hirotoshi Kubo, Junichiro Tojo, Hiroaki Saito, Masahito Onda
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Publication number: 20060118866Abstract: In a preferred embodiment of the present invention, first MOS transistors connected to first source electrodes and second MOS transistors connected to second source electrodes are arranged alternately next to each other on one chip. Different potentials are applied respectively to the first source electrodes and to the second source electrodes, and both of the MOS transistors are controlled with respect to an ON or OFF state by one gate terminal. Currents flow along surroundings of trenches, whereby on-resistance is reduced.Type: ApplicationFiled: November 16, 2005Publication date: June 8, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Masamichi Yanagida, Tadao Mandai
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Publication number: 20060065926Abstract: A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.Type: ApplicationFiled: September 21, 2005Publication date: March 30, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Hirotoshi Kubo, Junichiro Tojo, Hiroaki Saito, Masahito Onda, Satoshi Iwata, Masamichi Yanagida
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Publication number: 20060054970Abstract: In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.Type: ApplicationFiled: September 7, 2005Publication date: March 16, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Masamichi Yanagida, Hirotoshi Kubo, Junichiro Tojo, Hiraoki Saito, Masahito Onda